| CSE 140 Summer 2001: (tue & thu 5pm HSS 2250) |
| Text book: Contemporary Logic Design by Randy H. Katz |
| Instructor: |
Isaac Chu,
ichu@ece.ucsd.edu
Office hour @apm2331 Th 330-500pm & by appointment.
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| Teaching Assistants |
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Kyriakos Lakkas
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klakkas@cs.ucsd.edu
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tue 1-5pm
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|
Lam Pham
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l5pham@ieng9.ucsd.edu
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*mon 6-9pm, tue 1-3pm
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|
Marshal Dhillon
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marshal@ucsd.edu
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*mon 2-5pm,
tue 3-5pm
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Office hours will be at apm2331 (or apm2444 if unavailable)
* office hours changed to help prepare tuesdays' quizzes.
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Course work:
Objective of this course is to introduce digital components and digital systems
designs. Following are the subjects to be discussed this quarter:
- Switch Networks, Boolean Algebra, and K-maps.
- 2-Level Logic, Multi-level Logic
- Hazards, Multiplexer, and De-multiplexer
- CMOS - what's inside these logic gates
- Programmable Arrays of Logic Gates
- Sequential Logic Design: RS Latch, D-flip flop, JK-flip flop
- Counters
- State Machines Designs (Mealy and Moore)
- State Optimization
- Datapath and Control
- Arithmetic Circuits will be covered in
140L
practice hw problems :
- ch1(8,9,10,11)
- ch2(10,12,13,19)
- ch3(8de,16a,16b)
- ch4(11,15a)
- CMOS: (1) F= A(B+C)' (2) F=AB+C
- PLA & PAL: F1=A+B'C, F2=AC'+AB, F3=B'C+AC, F4=AC'+B'C
- ch6(11ac,13,16,17,18)
- ch7(10,12)
- ch8(22-state diagram)
- ch9(3,4)
Grading:
- 4 quizzes every tuesday (15% each - drop one lowest score)
- one report - 15% (due 8/2 thu) topic : memory, click here
- final exam - 40% (8/4 saturday 11am)
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