CSE 141L Lab # 3 - Design the "Dewey Decimal" architecture

Due May 16 during class.

This lab has two parts:

Part A is to design an Instruction Set Architecture for a simple processor. (Lab 4, the last lab, will be to implement the ISA using LogicWorks, and write and run two programs for the processor.)
Part B is to produce a timing diagram for a small circuit in LogicWorks. The main purpose of this lab is to make sure you are using the "official class technology".

You should do the lab in groups of up to four people. Four-person groups are encouraged, both because there will be a lot of work, and because it's good to learn to work with others.

Part A

You will design the instruction set architecture (ISA) for an 10-bit (yes, TEN-bit) processor, meaning that the instructions operate on data that is 10 bits long. The instructions will also be 10-bits long. Ten is a strange number of bits to use, but it should make an interesting project.

Let's call a ten-bit object a "Tyte". The computer will have a memory of up to 1024 Tytes (though the implementation you make will probably have only 256 Tytes).

The numbers you need to work with are unsigned (ten-bit) integers. This means that the bit string 0000000000 represents the integer 0, the Tyte 0000000001 represents 1, and so on, up to the largest representable integer, 1111111111, which is the decimal number 1023.

The ISA should be "general purpose", but you will only need to implement the instructions needed for two programs that you will write (in Lab 4):

Integer multiplication
This program should multiply two Tytes, producing a one-Tyte result. The two numbers being multiplied should be in memory locations 130 and 131, the answer should be put in memory location 129. If the answer is greater than the largest representable number (1023), then the "return code" (in location 128) should be set to 1, otherwise it should be 0. Here is a high-level description of the multiplication algorithm. Please note that this is simpler than what was described in class.
List maximum
Given a list of integers, this program should find the maximum element in the list. The length L of the list will be given in memory location 138 and a pointer to the list will be in location 139. For instance, if 138 contained "3" and 139 contained "25" then the list would be the three numbers in locations 25, 26, and 27. The program should find the largest element in the list and put its value into memory location 137. Also, a pointer to the maximum (or one of the maximum values if there is more than one occurrence) should be put into memory location 136.

Your ISA should have a "pause" instruction that halts execution, but leaves the PC ready to execute the next instruction (after the users pushes a "restart" button that will be part of your implementation)

You need to hand in a concise but complete description of your ISA. This should include:

A list of all the "architected registers" in your processor. This term refers to any hardware in the ISA that holds values from one cycle to the next. Probably you will have some number of registers $0, $1, ..., a program counter (PC), and perhaps a condition code (CC). You should also describe any registers that have special properties (for instance, in the MIPS architecture, $0 always holds the value 0.)
A description of each instruction. You should use a format similar to the MIPS instruction descriptions in the text starting on Page A-52, but with more complete descriptions. The descriptions should tell when the condition code is set (if your ISA uses a condition code), how the memory address used by a Load or Store instruction is computed, whether branches are PC-relative, and so on.
A startup program fragment. Suppose when you first turn on the computer, the program counter is initialized to "0", but the contents of the remaining architected registers are set to random numbers. Write the instructions that would be needed to load a register with the value that is stored in memory location 500 and then jump to the instruction in memory location 1000.

Part B

In Lab 4, you will build your processor in LogicWorks. The "official class technology" uses devices from the libraries listed here, and you should should use the following delays:

Devices in the primgate library: use delay 1 (this is the default, so you don't need to do anything).
The Clock Oscillator (in the primio library) should have a "high" time of 3 and a "low" time of whatever you need so that everything in your circuit settles down before the next cycles starts. For now, you can set "low" to 17, but you'll probably need to increase it later. See instructions below on how to set the clock times.
Devices in the primlogi library: set the delay to 3 (see below). I expect the gates you will need from here are the D Flip Flop, and assorted Registers,Adders, Multiplexors, and Decoders.
RAM, PROM and PLA's: set the delay to 10.

Note: Although it is possible to build a Mux or Decode out of simpler gates and end up with a device with delay less than 3, please don't bother. It's not that important to get a fast circuit, and it will only make your job more difficult. (One of the problems with LogicWorks is there's a limit on how big the circuit can be!)

How to set the delay

Copy the gate to the circuit.
Select it (by clicking on it)
In the "Simulate" menu, choose "Simulation Params"
Set the number (or the two numbers for clocks).

Timing diagrams

You should set the timing reference lines to the rising edges of clock signal. This is done by going to the "Simulate" menu, choosing "Trigger Setup", and then in the box labelled "Signal Value Condition" put the name of your clock in the "Signal" box, and "1" in the "Value" box. Also check off the "Reference line" item in the "Action" box.

What to do for Lab 3

This exercise is to make sure you have the right timing methodology. Using the official class technology, make a circuit that consists of a D Flip Flop, with the Set and Reset inputs attached to "1"'s, a Clock Oscillator connected to the "C" input, and a binary switch attached to the "D" input. The negated output (Q-bar) should go to a chain of five inverters. (The purpose of this is to slow down LogicWorks' simulations.)

Hand in a copy of the circuit, and a timing chart that shows the three signals: the clock, the switch, and the other output (Q) of the Flip Flop. You should run the clock for about 15 high's and low's of the clock, and during the time the clock is running, you should (by hand) flip the binary switch randomly up and down. The timing chart should show that whatever value is on the "D" input of the Flip Flop when the clock rises is the value that "Q" becomes when the clock falls.