Spring 2021
Instructor: Dean Tullsen
tullsen at cs dot ucsd dot edu
office hours by appointment
Kazem Taram, Samira Mirbagher, and Daniel Moghimi will be helping me out with the course in a variety of ways.
This is a paper reading course. We'll typically read 2 papers a week. Most will be presented by students.
I expect students to be enrolled for 2 units, s/u. To pass the class, you are expected to read the papers and come prepared to discuss, and to present at least one of the papers. Drop-ins are more than welcome.
Class meets W 5:00-6:20. If you're enrolled, find the info on canvas. If not, please contact me for zoom links.
I want to be open to directions the students want to take with this class, so any suggestions for papers you want to read, or specific topics you want to explore, please send them to me!
Rough Schedule (we'll put more detail in this soon):
| March 31 | Introduction. If you can please take a look at Chapters 1 and 2 of Principles of Secure Processor Architecture Design before class. | Dean |
| April 7 | Microarchitecture Side Channels: Cache Missing for Fun and Profit Jump Over ASLR: Attacking Branch Predictors to Bypass ASLR |
?? |
| April 14 | Side Channel mitigations: A Note on the Confinement Problem DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processor |
?? |
| April 21 | Transient Execution Side Channels: Spectre Attacks: Exploiting Speculative Execution RIDL: Rogue In-Flight Data Load |
?? |
| April 28 | Spectre mitigations: InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization |
?? |
| May 5 | Physical/Voltage Side Channels
: The EM Side-Channel(s) Plundervolt: Software-based Fault Injection Attacks against Intel SGX |
?? |
| May 12 | Oblivious Computation
: Path ORAM: An Extremely Simple Oblivious RAM Protocol Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing |
?? |
| May 19 | DRAM/Memory Security
: Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors TRRespass: Exploiting the Many Sides of Target Row Refresh |
?? |
| May 26 | FPGA Security
: Trusted Design in FPGAs FPGA-Based Remote Power Side-Channel Attacks |
?? |
| June 2 |
Architectural Support for Security
: Chapters 2 and 3 from: An Introduction to CHERI Cornucopia: Temporal Safety for CHERI Heaps |
?? |
Other Possible Papers. Please skim the paper for relevance to the class. Feel free to introduce other papers or topics.
TBD