\documentclass[letter, 12pt]{article}
\usepackage{graphicx}
\textwidth=14.9cm
\voffset -2.5cm
\hoffset -1.2cm
\textheight=24cm
\topmargin 2cm

%\pagestyle{empty}
\pagenumbering{arabic}

\begin{document}

\noindent
\textbf{\Large CSE140 HW 4, Due 11:59PM, Wed. 6/2/2021}
\newline

\noindent
{\bf
For the first three problems, we practice the usage of standard interconnect
components. The fourth problem covers a standard sequential component.
For the last problem, we practice system design processes.} \\

\noindent
1. (Decoders) Given three four-input Boolean functions

\indent
$f_1 (a,b,c,d) = \sum m(1,3,5,7,9) + \sum d(12,13,14,15)$,

\indent
$f_2 (a,b,c,d) = \sum m(1,5,7,12,15) + \sum d(3,8,14)$,

\indent
$f_3 (a,b,c,d) = \sum m(2,3,9,15) + \sum d(0,11,12)$.

\noindent
1.1. Implement the functions using a minimal network of 4:16 decoders and
OR gates.

\noindent
1.2. Implement the functions using a minimal network of 3:8 decoders and
OR gates.

\noindent
1.3. Implement the functions using a minimal network of 2:4 decoders and
OR gates.
\\

\noindent
2. (Multiplexers) Assume a dual-railed system, where you have access to any
variable and its complement.
Implement the following four-input Boolean function as indicated in each
of the following subproblems.

\indent
$f(a,b,c,d) = \sum m(0,2,7,12,13) + \sum d(3,5,6,8,15)$.

\noindent
2.1. Implement the function using a minimal network of 8:1 multiplexers.

\noindent
2.2. Implement the function using a minimal network of 4:1 multiplexers.

\noindent
2.3. Implement the function using a minimal network of 2:1 multiplexers.
\\

\noindent
3. Assume a dual-railed system, where you have access to any variable and
its complement. Given a four-input Boolean function

\indent
$f(a,b,c,d) = \sum m(0,2,3,5,11,13) + \sum d(4,7,10)$.

\noindent
3.1. Implement the function using a minimal network of 2:4 decoders and
OR gates.

\noindent
3.2. Implement the function using a minimal network of 4:1 multiplexers.

\noindent
3.3. Implement the function using a minimal network of 2:1 multiplexers.
\\

\noindent
4. Counter: Use standard modulo counters to design various counters.

\noindent
4.1 Given a modulo 16 counter, construct a 4 to 11 counter.

\noindent
4.2 Given a modulo 8 counter, construct a counter that counts in a sequence 0, 1, 5, 3, 4, 7,
with minimal networks of AND, OR gates.

\noindent
4.3 Construct a modulo 64 counter using modulo 8 counters.
\\

\noindent
5. System Designs: Implement the following algorithm:

\noindent
\begin{itemize}  \setlength\itemsep{-3pt}
\item [] Alg(X,Y,Z,start,U,done)
\item [] Input X[7:0], Y[7:0], Z[7:0], start;
\item [] Output U[7:0], done;
\item [] Local-object A[7:0], B[7:0], C[7:0];
\item [] S1: If start' goto S1;
\item [] S2: done  $\Leftarrow$  0  $\parallel$ A  $\Leftarrow$  X  $\parallel$ B  $\Leftarrow$  Y  $\parallel$  C $\Leftarrow$ Z;
\item [] S3: A  $\Leftarrow$  Inc(A) $\parallel$ B  $\Leftarrow$  Inc(B);
\item [] S4: If A'[7] goto S3  $\parallel$ B  $\Leftarrow$  Inc(B);
\item [] S5: If B'[7] goto S4  $\parallel$ C  $\Leftarrow$  Inc(C);
\item [] S6: If C'[7] goto S5  $\parallel$ A  $\Leftarrow$ Add(A,B);
\item [] S7: U  $\Leftarrow$  C  $\parallel$ done  $\Leftarrow$  1  $\parallel$ goto S1;
\item [] End Alg
\end{itemize}

\indent
5.1 Design a data subsystem that is adequate to execute the
algorithm and draw the schematic diagram.

\indent
5.2 Design a control subsystem and draw the state diagram.

\indent
5.3 Implement the control subsystem with a one-hot encoding
design. Draw the logic diagram. 

\end{document}