CSE141: Introduction to Computer Architecture

When & Where

Peterson Hall 110

Lecture: TuTh 3:30p - 4:50p

Discussion Section:
M 5:00p - 5:50p (WLH 2005) or
M 5:00p - 5:50p (SOLIS 104)


Hung-Wei Tseng
email: h1tseng+CSE141SP16 @ cs.ucsd.edu
Office: 3208
Office Hours: MTu 2p-3p or by appointment

Teaching Assistants

Amirsaman Memaripour
email: amemarip+cse141sp16@cs.ucsd.edu
Office: CSE B275
Office Hours: M 3p-4p or by appointment

Jian Yang
email: jiy092+CSE141SP16 @ cs.ucsd.edu
Office: CSE B240A
Office Hours: Th 2p-3p or by appointment

Akshatha Gangadharaiah
email: agangadh @ eng.ucsd.edu
Office: CSE B250A
Office Hours: W 5:30p - 6:30p or by appointment

Rizwan Ahmad
email: rmahmad @ eng.ucsd.edu
Office: CSE B260A
Office Hours: Tu 9a-10a or by appointment

Harsha Basavaraj
email: hbasavar @ eng.ucsd.edu
Office: CSE B260A
Office Hours: F 1p-2p or by appointment


Ka Ngai Chan

Mingshan Wang

Runping Wang

Please check the google calendar for tutor schedules


URL http://goo.gl/JJyrXp. This is just a reference for office hours. You should check Schedule and Slides for more details.

Course Discussion Board

TritonEd. Required reading. Get signed up. You should also be subscribed to the discussion forums for the course.
Piazza. Optional.



Course Description

This course will describe the basics of modern processor operation. Topics include computer system performance, instruction set architectures, pipelining, branch prediction, memory-hierarchy design, and a brief introduction to multiprocessor architecture issues.

This course is taught in tandem with CSE141L. Unless you have discussed it with you me, you should be in enrolled in both.

Text books

Required: Patterson & Hennessy, Computer Organization and Design: The Hardware/Software Interface, Patterson & Hennessy, Morgan Kaufmann, 5th Edition

Required: Other assigned readings throughout the quarter.

Optional: The History of Computing This a great set of lectures from a course taught at UCSD/UW/Berkeley three years ago. Most of them are by the folks that actually made the history (Steve Wozniak, Ray Ozzie, Gordon Bell, etc.)


Homework 15%

Homeworks will be assigned throughout the course. They are due on Tuesdays

Class participation 10%

We will be using clickers in the class!

Reading Quizzes 15%

We will have reading quizzes on TritonEd!

Midterm 25%

Final 35%

The final will be cumulative.

Additional notes about grades in this course:

  1. Your score will be available on TritonEd. Your final grade is the weighted average of these grades.
    We do our best to record grades accurately, but you should double-check.

  2. Errors in grading If you feel there has been an error in how an assignment or test was graded, you have one week from when the assignment is return to bring it to our attention. You must submit (via email to the instructor and the appropriate TAs) a written description of the problem. Neither I nor the TAs will discuss regrades without receiving an email from you about it first.
    For arithmetic errors (adding up points etc.) you do not need to submit anything in writing, but the one week limit still applies.

  3. For midterm and final, we do not regrade on a single problem. We will re-grade your whole test.

  4. Final grades If you have a problem with your final grade in the course, send me email and we can set up an appoinment to discuss it.

Schedule and Slides

DateTopicReadingsPre-release slidesSlidesDueNotes
2016/03/29 Introduction   Introduction   Demo
2016/03/31 ISA 2.1-2.14 ISA ISA (I) Reading quizzes for 2.1-2.14 due before class  
2016/04/05 ISA 2.17 ISA (II)   Demo
2016/04/07 Performance Evaluation 1.5-1.10 Performance Performance Reading quizzes for 1.1-1.10 due before class  
2016/04/12 Performance Evaluation   Performance (II) Homework 1 due before class Demo
2016/04/14 Single cycle processor 4.1-4.4 Single Cycle Processor Single Cycle Processor Reading quizzes for 4.1-4.4 due before class  
2016/04/19 Pipeline 4.5-4.9 Pipelined Processor Pipelined Processor Reading quizzes for 4.5-4.9 due before class
2016/04/21 Pipeline / Data Hazards   Pipelined Processor(II)    
2016/04/26 Pipeline / Control Hazards   Pipelined Processor(III) Homework 2 due before class
2016/04/28 Branch Prediction   Pipelined Processor(IV)   Demo
2016/05/03 Midterm review     Midterm Review Homework 3 due before class
2016/05/05 Midterm          
2016/05/10 Memory and caching 5.1-5.5 and 5.8 Memory Hierarchy/Cache Memory Hierarchy/Cache(I) Reading quizzes for 5.1-5.5 and 5.8 due before class Demo
2016/05/12 Memory and caching   Memory Hierarchy/Cache(II)    
2016/05/17 Memory and caching   Memory Hierarchy/Cache(III) Homework 4 due before class Demo
2016/05/19 Virtual Memory 5.7 Virtual Memory Virtual Memory Reading quizzes for 5.7 due before class  
2016/05/24 Modern Processor Design 4.10 Modern Processor Design Modern Processor Design  
2016/05/26 Introduction to multiprocessor 6.4-6.5 Multithreaded Processors Multithreaded Processors Reading quizzes for 6.4-6.5, 5.10 due before class Demo
2016/05/31 Heterogeneous Computing, Storage and Future Computer Architectures 6.3 and 6.6 Heterogeneous Computing, Storage and Future Computer Architectures Heterogeneous Computing and Future Computer Architectures Homework 5 due before class Demo
2016/06/02 Final Review   Final Review    
2016/06/06 Final          

Integrity Policy


Homework 1

Homework 2

Homework 3

Homework 4

Homework 5