Spring 2014 CSE 140L
Digital Systems Laboratory
(for both Section-A and Section-B)
by
Dr. Choon Kim
CSE Dept., UCSD
News & Updates
30. 06/17/14: [Dr. Kim] Midterm#2
& Letter Grade Guideline Information is available on
Ted(see Announcement and MyGrade).
29. 06/05/14: [Jason] My
tomorrow Fri.(6/6) office hour 10-12pm has been moved to 12-2pm.
28. 05/30/14: [Dr. Kim] Reminder: Fri.
06/06/14, Midterm#2 during lecture hour. It's a closed book
exam and 15 pts. total. Wish all the students a good luck on this last test!
27. 05/29/14: [Larry] My
Wed(6/4) 9-1pm office hour has been moved to Mon(6/2) 9-1pm (to help
students' LAB4 Demo better)
26. 05/21/14: [Jason] This week
only: F(5/23) 10-12pm has been cancelled
25. 05/20/14: [Dr. Kim] LAB#4 assigned.
Due = Tue. 2pm 06/03/14
24. 05/19/14: [Duy] Today M(5/19)
10-2pm has been cancelled due to emergency (makeup hour: this
week Wed. 5/21 9-12pm, 1-2pm)
23. 05/14/14: [Hyunwoo] This
week only: F(5/16) 9-10:10am has been cancelled(makeup hour: next
week Wed. 5/21 9-1pm)
22. 05/12/14: [Dr. Kim] A typo error was found and
corrected in Section 4.3 of LAB3 document.
"4.3) Credit Card input when hex[3:0]=3500 and LEDR
blinking......" was corrected to
"4.3) Credit Card input when hex[3:0]=3500 and LEDG blinking......"
Since our golden solution shows the correct behavior, I do not
expect anybody confused due to this. No direct inquiry from student
received yet. However if you got any point deduction solely due to this typo, come and prove to
me. I will be happy to correct your score if your case is acceptable.
21. 05/11/14: [Dr. Kim] Midterm#1
score available on TED. The exam paper is not returned to student but is kept
with Dr. Kim in his office. The student is allowed to review his/her exam paper
during Dr. Kim's office hour until the end of Spring quarter.
20. 05/07/14: [Dongbin(Vin)]
Permanent change from week of 05/12: T 11:30-2:30pm, Th 11:30-4:30pm
19. 05/06/14: [Dr. Kim] 1) Reminder: When
you use the golden solution, DO NOT forget to read the instruction, "Rules
when you use a golden solution" in LAB#1 document Sec.2. It can
help avoiding unnecessary confusion.
2) Each LAB report has no more than 10 pages excluding cover page.
18. 05/05/14: [Dr. Kim] LAB#3 assigned.
Due = Tue. 2pm 05/20/14
17. 05/01/14: [Dr. Kim] Reminder:
Tomorrow, Fri. 5/2, Midterm#1 during lecture hour. It's a closed book
exam and 15 pts. total. Wish all the students a good luck on this first test!
16. 04/29/14: [Hye Lim(Hailey)] This week only: T(4/29)
11:20-2pm, W(4/30) 11:30-12:50pm, Th(5/1) 11:20-3:20pm.
[Hyunwoo] This week only: W(4/30)
hours moved to Th(5/1) 9-12pm, F(5/2) 9-10:10am.
15. 04/28/14: [Dr. Kim] Reminder:
Student must bring student ID card to Midterm exam(for checking ID during exam).
14. 04/28/14: [Yingbai] This week only: M(4/28) 10:30-4:30pm,
Th(5/1) 11:30-1:30pm
13. 04/26/14: [Dr. Kim] A typo error was found and
corrected in PART4 of LAB2 document.
".......since the moment when SW[8] goes up(i.e.,
when Part4 selected)......" was corrected to
".......since the moment when SW[6] goes up(i.e., when Part4 selected)......"
Since this information has been clearly specified in Section 4 already, I do not
expect anybody confused due to this. No inquiry from student was reported
yet. If you got any point deduction solely due to this typo, come and prove to
me. I will be happy to correct your score if your case is acceptable.
12. 04/24/14: [Duy] This week(5/1&2) only:
Moving F.(5/2) 10-2pm into Th.(5/1) 11-3pm
11. 04/22/14: [Angie] This Wed(4/23) only:
W 2-4pm
10. 04/21/14: [Dongbin(Vin)] This week(4/21-25) only:
T(4/22) 11:30-1:30pm, Th(4/24) 11:30-3:30pm
09. 04/15/14: [Dr. Kim] LAB#2 assigned.
Due = Thu. 6pm 05/01/14
08. 04/14/14: [Dr. Kim] A new tutor, Sanjana Agarwal,
joined our tutor team starting from 4/14.
07. 04/13/14: [Yingbai] Permanent change from week of
4/14(3rd week): M 12-4pm, TTh 11:30-1:30pm
06. 04/11/14: [Zhihui(Vera)] Permanent change from week of
4/14(3rd week): T 9-12pm, W 1-3pm, Th 9-12pm.
[Dongbin] 4/14week(3rd week) only: M 9:30-12:30pm
1:30-3:30pm T 11:30-2:30pm
05. 04/09/14: [Hyunwoo] Permanent change from week of
4/14(3rd week): T 9-1pm, W 9-11:50am, F 9-10:10am.
04. 04/07/14: [Angie] This week only:
my Tue(4/8) office hour is 12-1:30pm and 2-3pm.
03. 04/07/14: [Daniel] This week only: my Fri(4/11) office hour
has one more hour, 9-2pm(to make up missing one hour today).
02. 04/06/14: [Hyunwoo] This week only:
my Wed(4/9) 9-1pm office hour was moved to Fri(4/11).
01. 04/04/14: [Dr. Kim] 1) First day of SP14 CSE140L(Sec-A & B).
2) LAB#1 assigned.
Due = Tue. 6pm 04/15/14
3) CSE3219LAB access code for SP14 CSE140L students available on TED
Course Description
Implementation with computer-aided design(CAD) tools for combinational logic
minimization and state machine synthesis. Hardware construction of a small
digital system. See http://www.cs.ucsd.edu/cse140L.
Instructor
Dr. Choon Kim, office: CSE3218, office phone: 858-246-0320, email:
chk034@eng.ucsd.edu
Office Hours(see tutor office hour section below).
About Choon Kim
Message from Instructor
Welcome to CSE140L class! The knowledge & skills that you will learn from
this class can be very useful in your engineering career in the future. Also the
LAB projects can be fun to do. However this class demands your
significant amount of effort and
real hard work. I wish all of you a good luck in my
class.
Websites
http://cseweb.ucsd.edu/classes/sp14/cse140L-ab/ For Syllabus,
News & Updates, Lecture notes, LAB
assignments, etc.
https://ted.ucsd.edu/webapps/login/ For Submitting LABReport, Checking grade,
Discussions among students , etc.
Course Information Sources
1. This course webpage and
instructor are
ONLY valid information sources for any
course-related issues such as LAB Projects, Reports, Grading, Exam or other
issues. If student has a question which is not answered on this course webpage(or
if an information from instructor is inconsistent
with the information on this course web page),
student should ask instructor to get a clear answer.
2. Therefore any excuse based on source other than above two
is NOT accepted by
instructor. For example, an excuse like "A tutor said this...", "A friend of
mine said that...", "I heard it from somebody who took this class before...",
etc., is not accepted.
3. Student is required to check this webpage
frequently, at least twice a day, to avoid missing
time-critical information.
Two sections in different time slot:
Section-A(F 4-6pm), and Section-B(F 6-8pm)
- Student must attend his/her
own registered section class.
- Student is NOT allowed to attend other section's class.
Missing class(Lecture, Discussion)
- The Lecture and the
Discussion are official part of this course. Student is required to attend
both.
- If student is not able to attend
regularly either Lecture
or Discussion for any reason(e.g., time conflict with other class enrolled), he/she
misses 50% of class meetings and, therefore, should NOT take this course.
- When student misses Lecture or
Discussion, he/she is responsible
to recover all the missing information as soon as possible. One suggested way is
that student must find a friend who attended the class and is willing to share
the class contents.
- Missing classes is one of common reasons of failure or
low grade in this course.
Tutors
Rules about tutors:
- Tutors are available for student. Student
may be able to get help from them. However following limitations are applied.
- Any
information from tutor must be treated by student as
an unconfirmed
or unverified
reference only. Student is responsible to check and confirm the correctness
& the validity of information obtained from tutor.
- Therefore any excuse by
student blaming tutor's help(e.g., "Tutor said this..." or "Tutor said that....", etc.) is
not
accepted by instructor.
-
The basic rule is:
Student, NOT tutor, is responsible for completing project and
other works.
Tutor location: CSE3219LAB (If the 3219LAB room is
reserved or occupied by other event, tutor may meet student at the lobby area in front of the CSE3226)
Office Hours: Tutor and Instructor office
hours can be changed whenever necessary. Student should
always check the latest office hour information first on this webpage if he/she wants to meet a specific
tutor or instructor.
Tutor:
Mon
Tue Wed Thu Fri
Angie Nguyen
12-3pm 12-2pm
12-3pm
(ann045@ucsd.edu)
Brian T Ly 11-1pm 3-6pm
3-6pm
(btly@ucsd.edu)
Daniel Kim 9-1pm
9-1pm
(jek014@ucsd.edu)
Dongbin(Vin) Koo 1:30-3:30pm 11:30-2:30pm
11:30-2:30pm
(dkoo@ucsd.edu)
Duy K Vu
10-2pm
10-2pm
(d8vu@ucsd.edu)
Hye Lim(Hailey)Park 11:20-3:20pm
11:20-3:20pm
(hlpark@ucsd.edu)
Hyunwoo(Harry) Cho
9-1pm 9-11:50am
9-10:10am
(hyc046@ucsd.edu)
Jason K Yohena 10-2pm
10-12pm
10-12pm
(jyohena@ucsd.edu)
Larry Huynh
9-1pm 9-1pm
(lahuynh@ucsd.edu)
Sanjana Agarwal 10-2pm 10-12pm
10-12pm
(s3agarwa
Timothy J Kua 1-3pm
4-7pm
4-7pm
(tkua@ucsd.edu)
Yingbai He 12-4pm 11:30-1:30pm 11:30-1:30pm
(y7he@ucsd.edu)
Zhihui(Vera) Xia
9-12pm 1-3pm
9-12pm
(zhxia@ucsd.edu)
Dr. Kim(at his office)
12-2pm 3-5pm
(chk034@eng.ucsd.edu)
Exams:
.
- There is NO makeup exam if student misses
exam. Missing exam gets zero(0) point.
- If student has an
acceptable valid reason to miss exam(e.g., medical emergency verified by doctor's letter &
document), he/she must discuss with Dr. Kim as soon as possible.
a) Midterm( Two Midterms -- See Class
Schedule below)
b) Final Exam( NO Final Exam )
Class Schedule(The
schedule can be changed if necessary)
------------------------------------------------------------------------------------------
Week #1 (04/04) Introduction to course overall, LAB HW, SW, doc information, CAD Process, LAB#1
assignment
Week #2 (04/11) Intro. to CMOS, Gates, Logic Design(Comb.
Logic), FPGA, Introduction to Verilog HDL
Week #3 (04/18) Comb. Ckt(cont'd), Sequential Ckt
Concept, Verilog HDL(cont'd),
LAB#2
assignment
Week #4 (04/25) Sequential Circuit Design, Verilog HDL(cont'd),
------------------------------------------------------------------------------------------
Week #5 (05/02) *** Midterm#1 during class ***, LAB#3 assignment
Week #6 (05/09) FSM,
Week #7 (05/16) FSM(cont'd),
Week #8 (05/23) Practical Sequential Logic Design,
LAB#4 assignment
Week #9 (05/30) Practical Sequential Logic Design(cont'd),
------------------------------------------------------------------------------------------
Week #10 (06/06) *** Midterm#2 during class ***
Textbook(HW FPGA Board) :
-
No textbook is required, but each student should prepare a HW FPGA Board(See HW
FPGA Board section below for details).
-
Student can purchase the
board anyway he/she wants. The bookstore normally has some boards
in stock, so it's good idea to check with bookstore before all the boards are
sold out.
- The textbook used in CSE140 class is a good reference for this CSE140L class.
Computer needed for class(Window
OS PC)
- Our CAD SW runs on Window
OS(not on Mac OS X).
- Student can use student's own PC or CSE3219
LAB PCs.
CSE3219 LAB Room
1. The CSE3219 LAB is
open 24 hours, 7 days a week. Access passcode to the LAB will be announced for
students on TED. The 3219LAB has Window PCs to be used by student. First read
CSE3219Lab General Policies
before using LAB.
2. CSE3219 LAB is ***a shared LAB*** with other classes and events.
Various hours/time slots are reserved for others frequently. Student
cannot use 3219 LAB room or LAB PCs when they are reserved for other
class or events.
If the 3219LAB room is reserved or
occupied by other event, tutor will meet students at the lobby area in front of the CSE3226. Student need to check the LAB Schedule
sheet posted on the LAB door or the event "CSE 3219" on Google Calendar
if available.
3. While student can check LAB anytime, I have reserved CSE3219LAB room 5-7pm M-Th for our
CSE140L class students(However, please remember a fact that the LAB is a shared
facility and our reserved time can be overridden
by more important or urgent event of department)
Class ID(CID)
-
An unique 3-digit number called Class ID(CID) will be assigned to each student.
- Check
your TED account grade window to find your CID.
- The CID will be used throughout the course to
identify a student. CID starts from 001 up to 300 for Section-A students, and
starts from 501 up to 800 for Section-B students.
HW FPGA Board & CAD SW tools
1. HW FPGA Board
Altera Cyclone II FPGA Starter Development
Board(a.k.a DE1
Board).
Each
student is responsible to prepare one working board for the class. Student can
purchase the board anyway he/she wants. The bookstore normally has
some boards in stock, so it's good idea to check with bookstore before all the
boards are sold out.
2. CAD SW(free download from Altera site --
see the link below)
Altera Quartus II Web Edition Software
v9.0 Service Pack 2 (works on Window,
not on Mac OS X) -- DO NOT use different version!
-
If student uses CSE3219 LAB PC, it has v9.0 SP2 SW installed already.
- If student uses his/her
own PC, download SW from the following Altera website, and
install it on your computer.
https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v90.jsp
The executable file name is "90sp2_quartus_free.exe" and the file size is about
1.31GB.
LAB Project(Working,
Submission and Demonstration)
Step 1. Working on LAB
project
- All LAB projects must be done by student
individually.
No group work is allowed(i.e., students are NOT allowed to pair up).
- Discussion of information
not directly related to the solution is
allowed between students(e.g., general discussion of Verilog, CAD SW, HW Kit, etc.).
However, sharing of
solution
or information directly related to the solution between
students is strictly prohibited.
- Advice: It is highly
recommended to start the
project as early as possible for better chance of successful completion.
It is not a good idea to delay
project until the LAST DAY of the project period.
You
may have a pretty good
chance of missing due time.
Step 2. Submission
of Report & Design files to TED system
2.1 Student must submit a file to Ted system first before making a
demonstration.
Each student should put following two files into a single ZIP file(ZIP file
name is "LxCyyy.zip"), and
submit it to TED system by
due date & time.
file#1) a PDF file of your LAB Report(file name is "ReportLxCyyy.pdf")
file#2) a ZIP file of your LAB Project design directory(file name is "ProjectLxCyyy.zip")
where, x=LAB
Number, yyy=your CID.
For example,
For LAB1, student with CID#009
should submit L1C009.zip which contains
ReportL1C009.pdf and ProjectL1C009.zip.
Another Example:
For LAB3, student with CID#196
should submit L3C196.zip which contains
ReportL3C196.pdf and ProjectL3C196.zip.
Notes: ---------
- DO NOT
CHANGE the contents of your LAB Report and
LAB Project Design AFTER you submit them.
- TED accepts your submission
only once per LAB. Resubmission is not
allowed by TED.
-
No late submission
is accepted by TED.
- If student
a)
misses submission
or b) submits an invalid file(s),
he/she will
receive zero(0)
point for the LAB regardless of Demonstration.
2.2
Contents of LAB#4 Report------------------------------------------------------------
1) Use this
LAB4_Report_cover_page.docx The report
has no more than 10 pages excluding cover page.
2) Procedural description of work
done to complete the project
3) ***ONLY UPDATED PART*** of Verilog HDL
codes
4) ***ONLY UPDATED PART*** of State
Diagram of your design
5) A screen copy of Compilation
Report - Flow Summary(Clearly mark the Percentage(%) value of "Total logic
elements")
Contents of LAB#3 Report------------------------------------------------------------
Use this
LAB3_Report_cover_page.docx The report has no more than 10 pages
excluding cover page.
a) Procedural description of work done to complete the project
b) Complete Verilog HDL codes of your design(use
small fonts, multiple columns, multiple sides, etc. to save pages)
c) State Diagram of your design
d) A screen copy of Compilation Report - Flow Summary(Clearly mark the
Percentage(%) value of "Total logic elements")
Contents of LAB#2 Report------------------------------------------------------------
1) Use this LAB2_Report_cover_page.docx
2) Provide the followings in your
report.
a) Your work description(i.e., Describe what &
how you did in detail to complete the Parts in LAB#2)
b) A Flowchart drawing of your design(similar to a Flowchart when you
write a SW programming codes)
This is a graphical presentation of your LAB#2 work using the
flowchart format. Each student's presentation would be different depending
his/her work flow. There is, therefore, no standard solution or example. If you
are not familiar with the concept of flowchart, see
http://en.wikipedia.org/wiki/Flowchart
c) Complete Verilog Codes
d) Flow Summary in Compilation Report. Clearly mark the Percentage(%)
value of "Total logic elements"
e) Timing Analyzer Summary in Compilation Report. Clearly mark the
"Worst-case tco" row
Contents of LAB#1 Report------------------------------------------------------------
1) Use this LAB1_Report_cover_page.docx
2) The Report must be written well and clean enough for grader to understand it
easily in order to receive any credit. It has no more than 10 pages
excluding cover page
3) You should provide the followings
in the report for LAB#1.
a) Your work description(i.e., Describe what &
how you did in detail to complete the Parts in LAB#1)
b) Schematic diagram(hint: There are many different ways to capture the
diagram and paste it on your report. You can do any of them. )
c) Functional simulation diagram (hint: similar to the one shown in the example diagram in
the LAB#1 Document)
d) Timing simulation
diagrams. You must show at least one timing delay value on your waveform, like
the one shown in the example diagram in the LAB#1 Document
e) Timing Analyzer Summary(hint: it is available after you compile
your design successfully)
Step 3. Demonstration
of your project to Demo Reviewer(instructor or tutor)
3.1. A student who
made a submission to TED is allowed to demonstrate
his/her design to Demo Reviewer(instructor or tutor) by due
date &
time.
Notes: ---------
- DO NOT
CHANGE the contents of your LAB Report and
LAB Project Design AFTER you submit them
to TED.
-
The LAB
Project design on demonstration
must be the same one
which was submitted to
TED. Otherwise it is regarded as
cheating and
zero(0) point
will be assigned to student.
- Demonstration is performed
during office
hours with first-come, first-served basis. No appointment
will be made.
- No late Demo is allowed.
No
defective malfunctioning DE1 board is allowed for Demo.
- If a student
misses Demonstration,
he/she will
get zero(0) point
for the LAB regardless of the submission to TED.
3.2 Student must bring a
hardcopy of LAB Report to
demo reviewer(instructor or
tutor) to start demonstration.
3.3 For demonstration, DE1 board should have been programmed with
your design using AS(Active Serial)
method, not JTAG method.
3.4 During LAB Project Demonstration,
-
NO reprogramming of DE1
board is allowed during demonstration.
-
All the Parts of a LAB
project should be tested continuously without any interruption of reprogramming.
-
Only exception of this rule is LAB4(which may require reprogramming during demo.).
Grading
1. 100 points total:
All LABs = 70 points(10 points for LAB#1, 20
points for each of remaining three, LAB#2-4)
All exams
= 30 points
2. LAB#1:
a) 5 points for Demonstration. The student score is determined by
tutor/instructor based on the quality of LAB Demo output result.
b) 5 points for a Report. The student score is determined by
tutor/instructor based on the quality of LAB Report.
LAB#2-4:
a) 15 points for Demonstration. The student score is determined by
tutor/instructor based on the quality of LAB Demo output result.
b) 5 points for a Report. The student score is determined by
tutor/instructor based on the quality of LAB Report.
3. NO Partial Credit Grading Policy
- Each LAB project
consists of
several Parts(for example, LAB#1 may have five Parts).
- You will get either
full score or
zero(0) on
each Part of LAB.
NO partial score is
assigned to a Part.
- A full core is given only if
all required features of the Part are implemented and
demonstrated correctly. Otherwise zero(0) will be assigned.
- A partial score, if
given, is a clerical error and will be converted to zero(0) point.
- An
exception can be made
by instructor only in very rare special circumstance
4. A plus(+) and minus(-) grading scheme will be used in the
final letter grade assignment(e.g., A+ A A-, B+ B B-, C+ C C-, etc.).
Academic Dishonesty & Student Conduct Policy
As student in this offering of CSE 140L, you are expected to know and abide by
the UCSD Policy on Integrity of Scholarship (as described in the
Student Conduct
Code in the UCSD General Catalog), the Jacobs School of Engineering
Student
Honor Code, and the course policy described here.
Any student violating UCSD's Academic Dishonesty or UCSD's Student Conduct
policies will earn an 'F' in the course and will be reported to their college
Dean for administrative processing. Committing acts that violate Student Conduct
policies that result in course disruption are cause for suspension or dismissal
from UCSD.
--------------------- The End ------------------