WARNING: Information on this page is NOT valid
until Friday 4/4/14(the first day of class meeting). It is under
construction.
Spring 2014 CSE 140L
Digital Systems Laboratory
(for both sections-A & section-B)
by
Dr. Choon Kim
CSE Dept., UCSD
News & Updates
Course Description
Implementation with computer-aided design(CAD) tools for combinational logic
minimization and state machine synthesis. Hardware construction of a small
digital system. See http://www.cs.ucsd.edu/cse140L.
Instructor
Dr. Choon Kim, office: CSE3218, office phone: 858-246-0320, email:
chk034@eng.ucsd.edu
Office hours(see tutor section below)
Message from Instructor
Welcome to CSE140L class! The knowledge & skills that you will learn from
this class can be very useful in your engineering career in the future. Also the
LAB projects can be fun to do. However this class demands your
significant amount of effort and
real hard work. I wish all of you a good luck in my
class.
Websites
http://cseweb.ucsd.edu/classes/sp14/cse140L-ab/ For Syllabus,
News & Updates, Lecture notes, LAB
assignments, etc.
https://ted.ucsd.edu/webapps/login/ For Submitting LABReport, Checking grade,
Discussions among students , etc.
Course Information Sources
1. This course webpage and
instructor are
ONLY valid information sources for any
course-related issues such as LAB Projects, Reports, Grading, Exam or other
issues. If student has a question which is not answered on this course webpage(or
if an information from instructor is inconsistent
with the information on this course web page),
student should ask instructor to get a clear answer.
2. Therefore any excuse based on source other than above two
is NOT accepted by
instructor. For example, an excuse like "A tutor said this...", "A friend of
mine said that...", "I heard it from somebody who took this class before...",
etc., is not accepted.
3. Student is required to check this webpage
frequently, at least twice a day, to avoid missing
time-critical information.
Two sections in different time slot: Section-A(F 4-6pm) and Section-B(F 6-8pm)
- Student must attend his/her
own registered section class. Student is not allowed to attend other
section's class.
Missing class(Lecture, Discussion)
- The Lecture and the
Discussion are official part of this course. Student is required to attend
both for this class.
- If a student is not able to attend
regularly either Lecture
or Discussion for any reason(e.g., time conflict with other class enrolled), he/she
should NOT take this course.
- When a student misses Lecture or
Discussion in an emergency situation, he/she is responsible
to recover all the missing information as soon as possible.
- It was known from past experience that missing or skipping a
class is one of common reasons of failure or
low grade in this course.
Tutors
Rules about tutors:
- Tutors are available for student. Student
may be able to get help from them. However following limitations are applied.
- Any
information from tutor must be treated by student as
an unconfirmed
or unverified
reference only. Student is responsible to check and confirm the correctness
& the validity of information obtained from tutor.
- Therefore any excuse by
student blaming tutor's help(e.g., "Tutor said this..." or "Tutor said that....", etc.) is
not
accepted by instructor.
-
The basic rule is:
A student, NOT tutor, is responsible for completing project and
others.
Tutor location: CSE3219LAB (If the 3219LAB room is
reserved or occupied by other event, tutor may meet student at the lobby area in front of the CSE3226)
NOTE: Tutor and Instructor office
hours can be changed when an unexpected time conflict happens. Student should
always check the latest office hour list first if he/she wants to meet a specific
tutor or instructor.
Tutor List and Office hours:
Mon
Tue Wed
Thu
TBD
Exams:
schedule is TBD.
a) Midterm(multiple midterms may be given)
b) Final Exam(may or may not be
given -- TBD)
- There is NO makeup exam if student misses
exam. Missing exam gets zero(0) point. If student has an
acceptable valid reason(e.g., medical emergency verified by doctor's letter &
document), he/she must discuss with Dr. Kim as soon as possible.
Class Schedule(The
schedule can be changed if necessary)
------------------------------------------------------------------------------------------
Week #1 (04/04) Introduction to course overall, LAB HW, SW, doc information, CAD Process, LAB#1
assignment
Week #2 (04/11) Intro. to CMOS, Gates, Logic Design(Comb.
Logic), FPGA, Introduction to Verilog HDL
Week #3 (04/18) Comb. Ckt(cont'd), Sequential Ckt
Concept, Verilog HDL(cont'd),
LAB#2
assignment
Week #4 (04/25) Sequential Circuit Design, Verilog HDL(cont'd),
------------------------------------------------------------------------------------------
Week #5 (05/02) *** midterm during class ***, LAB#3 assignment
Week #6 (05/09) FSM,
Week #7 (05/16) FSM(cont'd),
LAB#4 assignment
Week #8 (05/23) Practical Sequential Logic Design,
Week #9 (05/30) Practical Sequential Logic Design(cont'd),
------------------------------------------------------------------------------------------
Week #10 (06/06) *** midterm during class ***
Textbook(HW FPGA Board) :
No textbook is required, but each student should prepare a HW FPGA Board(See HW
FPGA Board section below for details). Checking UCSD Bookstore for
available board is a good idea to start. The textbook used in CSE140 class is a good reference for this CSE140L class.
Computer needed for class(Window
OS PC, not Mac OS)
- Window OS PC is required since our CAD SW does run on Window
OS only, not on Mac OS.
- Student can use either
student's own PC or CSE3219
LAB room PCs.
(In the past, it was observed
that some Mac students installed Window OS on Mac as guest OS, and installed CAD
SW, and used it. It may or may not work. Note that there will be no technical
support or help from instructor or tutors since we are not an expert on that
approach.)
CSE3219 LAB Room
1. The CSE3219 LAB is
open 24 hours, 7 days a week. Access method to the lab will be announced for
students. The 3219LAB has Window PCs to be used by student. First read
CSE3219Lab General Policies
before using LAB.
2. CSE3219 LAB is ***a shared LAB*** with other classes and events.
Various hours/time slots are reserved for others frequently. Student
cannot use 3219 LAB room or LAB PCs when they are reserved for other
class or events.
If the 3219LAB room is reserved or
occupied by other event, tutor will meet students at the lobby area in front of the CSE3226. Student need to check the LAB Schedule
sheet posted on the LAB door or the event "CSE 3219" on Google Calendar
if available.
3. While student can try anytime, I have reserved LAB room 5-7pm M-Th for our
CSE140L class students(However, please remember a fact that the LAB is a shared
facility and our reserved time can be overridden
by more important or urgent event of department)
Class ID(CID)
An unique 3-digit number called Class ID(CID) will be assigned to each student. Check
your TED account grade window to find your CID. The CID will be used throughout the course to
identify a student. CID starts from 001 to the number of students enrolled(e.g.,
249, etc.)
HW FPGA Board & CAD SW tools
1. HW FPGA Board
Altera Cyclone II FPGA Starter Development
Board(a.k.a DE1
Board).
Each
student is responsible to prepare one working board for the class. Student can
buy the board anyway he/she wants. The bookstore normally has
some, so student can check with them before sold out.
2. CAD SW(free download from Altera site --
see the link below)
Altera Quartus II Web Edition Software
v9.0 Service Pack 2 (works on Window 7/8,
Vista, XP) -- DO NOT use different version! (e.g., later version).
-
If student uses CSE3219 LAB PC, it has SW installed already.
- If student uses his/her
own PC, download it from following Altera website, and
install it on your computer.
https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v90.jsp
The executable file name is "90sp2_quartus_free.exe" and the file size is about
1.31GB.
LAB Project(Working,
Submission and Demonstration)
Step 1. Working on LAB
project
- All LAB projects must be done by student
individually.
No group work is allowed(i.e., students are NOT allowed to pair up).
- Discussion of information
not directly related to the solution is
allowed between students(e.g., general discussion of Verilog, CAD SW, HW Kit, etc.).
However, sharing of
solution
or information directly related to the solution between
students is strictly prohibited.
- Advice: It is highly
recommended to start the
project as early as possible for better chance of successful completion.
It is not a good idea to delay
project until the LAST DAY of the project period.
You
may have a pretty good
chance of missing due time.
Step 2. Submission
of Report & Design files to TED system
2.1 Student must submit a file to Ted system first before making a
demonstration. Each student should put following two files into a single ZIP file(file
name is "LxCyyy.zip"), and
submit it to TED system by
Submission Due date & time.
file#1) a PDF file of your LAB Report(file name is "ReportLxCyyy.pdf")
file#2) a ZIP file of your LAB Project design directory(file name is "ProjectLxCyyy.zip")
where, x=LAB
Number, yyy=your CID.
Example: For LAB1, student with CID#009
should submit L1C009.zip which contains
ReportL1C009.pdf and ProjectL1C009.zip.
Example: For LAB3, student with CID#196
should submit L3C196.zip which contains
ReportL3C196.pdf and ProjectL3C196.zip.
Notes: ---------
- DO NOT
CHANGE the contents of your LAB Report and
LAB Project Design AFTER you submit them.
- TED accepts your submission
only once per LAB. Resubmission is not
allowed by TED.
- No late
submission is accepted by TED.
-
If a student a)
misses submission
or b) submits an invalid, not-working or nonfunctioning
file(s), he/she will
receive zero(0) point for the
LAB regardless of Demonstration.
If student has an acceptable valid reason(e.g., medical emergency verified by doctor's letter &
document), he/she must discuss with Dr. Kim as soon as possible.
2.2
Contents of LAB#4 Report------------------------------------------------------------
1) Use this
LAB4_Report_cover_page.docx (note: You
have to put the submission time stamp on hard-copy cover page
to demonstrate. You can copy & paste your submission time stamp from
[Review Submission History] window on Ted, e.g., Submission
( November 22, 2013 2:47:41 PM PST ). You don't put this
submission time stamp on zip file when submitting. )
2) Procedural description of work
done to complete the project
3) ***ONLY UPDATED PART*** of Verilog HDL
codes
4) ***ONLY UPDATED PART*** of State
Diagram of your design
5) A screen copy of Compilation
Report - Flow Summary(Clearly mark the Percentage(%) value of "Total logic
elements")
Contents of LAB#3 Report------------------------------------------------------------
1) Use this
LAB3_Report_cover_page.docx
2) Procedural description of work done to complete the project
3) Verilog HDL codes of your design
4) State Diagram of your design
5) A screen copy of Compilation Report - Flow Summary(Clearly mark the
Percentage(%) value of "Total logic elements")
Contents of LAB#2 Report------------------------------------------------------------
1) Use this LAB2_Report_cover_page.docx
2) Provide the followings in your
report.
a) Your work description(i.e., Describe what &
how you did in detail to complete the Parts in LAB#2)
b) A Flowchart drawing of your design(similar to a Flowchart when you
write a SW programming codes)
This is a graphical presentation of your LAB#2 work using the
flowchart format. Each student's presentation would be different depending
his/her work flow. There is, therefore, no standard solution or example. If you
are not familiar with the concept of flowchart, see
http://en.wikipedia.org/wiki/Flowchart
c) Complete Verilog Codes
d) Flow Summary in Compilation Report. Clearly mark the Percentage(%)
value of "Total logic elements"
e) Timing Analyzer Summary in Compilation Report. Clearly mark the
"Worst-case tco" row
Contents of LAB#1 Report------------------------------------------------------------
1) The Report must be written well and clean enough for grader to understand it
easily in order to receive any credit. It has no more than 10 pages
excluding cover page.
2) Use this LAB1_Report_cover_page.docx
3) You should provide the followings
in the report for LAB#1.
a) Your work description(i.e., Describe what &
how you did in detail to complete the Parts in LAB#1)
b) Schematic diagram
c) Functional simulation diagram (hint: similar to the one shown in the example diagram in
the LAB#1 Document)
d) Timing simulatio
diagrams. You must show at least one timing delay value on your waveform, just like
the one shown in the example diagram in the LAB#1 Document
e) Timing Analyzer Summary(hint: it is available after you compile
your design successfully)
Step 3. Demonstration
of your project to Demo Reviewer(instructor or tutor)
3.1. A student who
made a submission to TED is allowed to demonstrate
his/her design to Demo Reviewer(instructor or tutor) by
Demo
Due date &
time.
Notes: ---------
- DO NOT
CHANGE the contents of your LAB Report and
LAB Project Design AFTER you submit them.
- The LAB
Project design showing on demonstration
must be the same one
which was submitted to
TED. Otherwise it is regarded as
cheating and
zero(0) point
will be assigned to student.
- Demonstration is performed
during office
hours with first-come, first-served basis. No appointment for demonstration
will be made.
- No late Demo is allowed. No
defective malfunctioning DE1 board is allowed for Demo.
- If a student
misses Demonstration,
he/she will
get zero(0) point for the LAB
regardless of the submission. If student
has an acceptable valid reason(e.g., medical emergency verified by doctor's letter &
document), he/she must discuss with Dr. Kim as soon as possible.
3.2 Student must bring a
hardcopy of LAB Report to
demo reviewer(instructor or
tutor) to start demonstration.
3.3 For demonstration, DE1 board should have been programmed with
your design using AS(Active Serial)
method, not JTAG method.
3.4 [ During LAB Project Demonstration ]
- NO reprogramming of DE1
board is allowed during demonstration.
-
All the Parts of a LAB
project should be tested continuously without any interruption of reprogramming.
-
Only exception of this rule is LAB4(which may require reprogramming during demo.).
Grading
1. 100 points total:
All LABs = 70 points(10 points for LAB#1, 20
points for each of remaining three, LAB#2-4)
All exams
= 30 points
2. LAB#1:
a) 5 points for Demonstration. The student score is determined by
tutor/instructor based on the quality of LAB Demo output result.
b) 5 points for a Report. The student score is determined by
tutor/instructor based on the quality of LAB Report.
LAB#2-4:
a) 15 points for Demonstration. The student score is determined by
tutor/instructor based on the quality of LAB Demo output result.
b) 5 points for a Report. The student score is determined by
tutor/instructor based on the quality of LAB Report.
3. NO Partial Credit Grading Policy(exception
can be made by instructor in special circumstance)
- Each LAB project
consists of
several Parts(for example, LAB#1 may have five Parts).
- You will get either
full score or
zero(0) on each
Part of
LAB. NO partial score is assigned to a Part.
- A full core is given only if
all required features of the Part are implemented and
demonstrated correctly. Otherwise zero(0) will be assigned.
- A
partial score, if given, is a clerical error and will be converted to zero(0)
point.
4. A plus(+) and minus(-) grading scheme will be used in the
final letter grade assignment(e.g., A+ A A-, B+ B B-, C+ C C-, etc.).
Academic Dishonesty & Student Conduct Policy
As student in this offering of CSE 140L, you are expected to know and abide by
the UCSD Policy on Integrity of Scholarship (as described in the
Student Conduct
Code in the UCSD General Catalog), the Jacobs School of Engineering
Student
Honor Code, and the course policy described here.
Any student violating UCSD's Academic Dishonesty or UCSD's Student Conduct
policies will earn an 'F' in the course and will be reported to their college
Dean for administrative processing. Committing acts that violate Student Conduct
policies that result in course disruption are cause for suspension or dismissal
from UCSD.
--------------------- The End ------------------