There are two ways to get an "A" in this class. One is to implement a
working pipelined MIPS processor by the end of the quarter that
executes simple programs compiled using the GCC cross compiler. This
is the grading option you should strive for. You can get an "A+" by
adding some interesting and exciting feature to your processor during
the final lab.
Doing well (i.e., getting an "A" or "A+") in the course will also
demonstrate your ability to build a large, complex computer system, and
it gives me a concrete and compelling reason to recommend you for jobs
(or graduate school positions) that require those kinds of skills.
The other way to get a good grade is to do well on the labs. If your
processor doesn't turn out as well, I will consider your performance on
the labs and participation (see below). Your grade will be at
least the maximum of the "your processor works" grade and the lab
assignment grade.
In addition to the labs, you should be an active contributer to the web
board. The tools are challenging and sometimes buggy. Your classmates
(in addition to the course's staff) are an excellent resource for help
with the tools.
This class is about doing. You will learn almost everything
you learn in this class by doing it. This means that you (or your
team) must do all your own work. As long as you meet this criteria,
you can consult with and discuss your project with other groups. We
have structured the course (by not having a curve) so that there is no incentive to be stingy
with your knowledge of the tools or in sharing your expertise with your
classmates.
Late lab write ups If you cannot complete your lab on time, you
can turn it in late, but your grade will be penalized. The penalty is
one letter grade per 24 hours extension. Up to 2 extensions are
possible. For example, if the labs are due at 5pm, you have until 5pm
the next day to turn it in with one letter grade penalty, and until 5pm
the day after to turn it in with a two letter grade penalty, and so on.
Keep in mind that even if your lab write up is late, you are still
responsible for completing the lab, since the labs build on one
another.
Items in the schedule more that one week in the future are subject to
change. Check back for updates for the assigned readings, etc. The date
for the midterm will not change, however. Nor will deadlines for
homeworks/projecsts that have been assigned be move earlier.
I will post the slides for most lectures. Since the slides contain
material I am not allowed to distribute publically, they are only
available from on campus or via the campus proxy. Instructions for
setting up the proxy can be
found here.
Using the proxy is useful in general, since it gives you full access to
the libraries and other resources from off campus.
| Date |
Topic |
Readings |
Slides |
Due |
Notes |
| Monday,
April 01 |
Administrivia; Overview of the course; Lab 1 assigned; Verilog I |
|
00_Introduction.key.pdf |
|
Tips for using Altera Tools
|
| Monday,
April 08 |
Verilog II; datapath and control design. Lab 2 preview. Lab 1 due |
|
02-Verilog2.pdf,
03_ImplementingMIPS.pdf
|
|
Lab 1 is due at 3PM on the Monday the 8th |
| Monday,
April 15 |
Verilog II; datapath and control design. Lab 3 preview. Lab 2 due |
|
04_ControlAndLab3-sp13.pdf |
Project 2;
|
|
| Monday,
April 22 |
Verilog II; datapath and control design; Lab 4: Branches preview. Lab 3 due |
|
05_Lab4.pdf |
Project 3;
|
|
| Monday,
April 29 |
Lab 4 questions |
|
|
|
|
| Monday,
May 06 |
Lab 5: 5 Stage preview, Lab4 Due |
|
06_Lab5.pdf |
Project 4;
|
|
| Monday,
May 13 |
Lab 5 questions |
|
|
|
|
| Monday,
May 20 |
Lab 6 Preview |
|
|
|
|
| Monday,
May 27 |
Memorial Day |
|
|
|
|
| Tuesday,
May 28 |
Lab 5 Due |
|
|
Project 5;
|
|
| Monday,
June 03 |
Lab questions |
|
|
|
|
| Monday,
June 10 |
Lab 6 Due |
|
|
|
|
