cse240c: Advanced Microarchitecture

Warren Lecture Hall 2204
Lectures Tue. & Thu., 8:00-9:20
Spring, 2013
Shortcuts: Schedule Homeworks

Instructor

Steven Swanson

Email:

swanson

cs.ucsd.edu

IM (not email): professorswanson@{AIM, Yahoo!, google talk, MS Messenger}
Office: EBU3B 3212
Office Hours: By appointment
UCSD homepage

Course Description

This course will cover advanced topics in processor microarchitecture. We will cover both the "latest and greatest" as well as the "oldies but goodies" in both commercial processors and architecture research. We will learn answers to questions like:

What are {super,multi,data,synchro,chrono,wave}scalar and why is everyone always talking about them?
How many pipeline stages does it to take to melt a pentium?
What do natural selection and branch prediction have to do with each other?
How do you design a processor to fit into your eyeball without cooking your brain?

Please acquaint yourself with the auxillary web page. It has the link to the paper summary submission page and the slide repository.

Text books

Required: Assigned readings throughout the quarter. See the schedule below

Grading

Note that 66% of you grade is determined by preparing for and participating in class.

Paper summaries	33%	You will summarize each paper we read in class. Summaries are due 20 minutes before class begins. No exceptions. This means there is no reason to be late for class to complete your summary.
Class participation	33%	This class is discussion driven, so must come prepared to discuss the material. This includes showing up. You should contribute to the discussion very nearly every day.
In class presentations	33%	In lieue of exams, each of you prepare and present two presentations on topics we will cover.

Schedule

Items in the schedule more that one week in the future are subject to change. Check back for updates for the assigned readings, etc. Deadlines for homeworks/projecsts that have been assigned be not be moved earlier.

I will post the slides for the lectures once I receive them from the presenter.

Date	Topic	Readings
Tuesday, April 2	Administrivia.
Thursday, April 4	Historical perspectives	Paper 1: Cramming More Components Onto Integrated Circuits, G.E. Moore, Proceedings of the IEEE 86(1):82-85, Jan 1998 link. Paper 2: The history of the microcomputer-invention and evolution, S. Mazor, Proceedings of the IEEE 83(12):1601-1608, Dec 1995 link. Additional readings if you are interested: A History of Microprocessor Development at Intel, R.N. Noyce and M.E. Hoff, Micro, IEEE 1(1):8 -21, feb. 1981 link. A 4096-bit dynamic MOS RAM, J. Karp, W. Regitz, and S. Chou, Solid-State Circuits Conference. Digest of Technical Papers. 1972 IEEE International XV: 10-11, Feb 1972 link. A three transistor-cell, 1024-bit, 500 NS MOS RAM, W. Regitz and J. Karp, Solid-State Circuits Conference. Digest of Technical Papers. 1970 IEEE International XIII: 42-43, Feb 1970 link. Design of ion-implanted MOSFET's with very small physical dimensions, R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous, and A.R. LeBlanc, Solid-State Circuits, IEEE Journal of 9(5): 256-268, Oct 1974 link. The future of wires, R. Ho, K.W. Mai, and M.A. Horowitz, Proceedings of the IEEE 89(4):490-504, Apr 2001 link. A whole issue of IEEE Solid-State Circuits Society News about Dennardian Scaling. link.
Tuesday, April 9	Historical perspectives	Paper 3: Architecture of the IBM System/360, G. M. Amdahl, G. A. Blaauw, and Jr. F. P. Brooks, :17-31, 2000 link. Paper 4: Parallel operation in the control data 6600, James E. Thornton, :5-12, 1995 link. Additional readings if you are interested: Design of a Computer -- The Control Data 6600, James E. Thornton, link. Considerations in Computer Design - Leading up to the Control Data 6600, James E. Thornton, , 1963 link. IBM's 360 and early 370 systems, Emerson Pugh, Lyle R. Johnson, and John H. Palmer MIT Press, 1991.
Thursday, April 11	Vectors	Paper 5: The CRAY-1 computer system, Richard M. Russell, Commun. ACM 21(1):63-72, 1978 link. Paper 6: Tarantula: a vector extension to the alpha architecture, R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec, Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on:281-292, 2002 link. Additional readings if you are interested: An analysis of the Cray-1 computer, Richard L. Sites, ISCA '78: Proceedings of the 5th annual symposium on Computer architecture, New York, NY, USA, 1978, pages 101-106 link.
Tuesday, April 16	Slippage	TBA
Thursday, April 18	Unconventional OOO exeuction	Paper 7: The WaveScalar architecture, Steven Swanson, Andrew Schwerin, Martha Mercaldi, Andrew Petersen, Andrew Putnam, Ken Michelson, Mark Oskin, and Susan J. Eggers, ACM Trans. Comput. Syst. 25(2):4, 2007 link (Sections 1-4 only). Paper 8: Monsoon: an explicit token-store architecture, G.M. Papadopoulos and D.E. Culler, Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on:82-91, May 1990 link. Additional readings if you are interested: Critical issues regarding HPS, a high performance microarchitecture, Y. N. Patt, S. W. Melvin, W. M. Hwu, and M. C. Shebanow, SIGMICRO Newsl. 16(4):109-116, 1985 link. First version of a data flow procedure language, J. B. Dennis, Programming Symposium, Proceedings Colloque sur la Programmation, London, UK, 1974, pages 362-376.
Tuesday, April 23	Reliability	You can choose 2 of the following three paper, if you are presenting that day. Paper 9: Transient fault detection via simultaneous multithreading, Steven K. Reinhardt and Shubhendu S. Mukherjee, SIGARCH Comput. Archit. News 28(2):25-36, 2000 link. Paper 10: DIVA: a reliable substrate for deep submicron microarchitecture design, Todd M. Austin, MICRO 32: Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, Washington, DC, USA, 1999, pages 196-207 link. Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor, Christopher Weaver, Joel Emer, Shubhendu S. Mukherjee, and Steven K. Reinhardt, ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture, Washington, DC, USA, 2004, page 264 link. Additional readings if you are interested: A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor, Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steven K. Reinhardt, and Todd Austin, MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC, USA, 2003, page 29 link.
Thursday, April 25	Circuit-level microarchitectural issues	Paper 11: ReCycle:: pipeline adaptation to tolerate process variation, Abhishek Tiwari, Smruti R. Sarangi, and Josep Torrellas, ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture, New York, NY, USA, 2007, pages 323-334 link. Paper 12: Razor: a low-power pipeline based on circuit-level timing speculation, D. Ernst, Nam Sung Kim, S. Das, S. Pant, R. Rao, Toan Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on: 7-18, Dec. 2003 link.
Tuesday, April 30	No class	TBA
Thursday, May 2	Capabilites	Paper 25: Chapters 1 and 9 of Capability-Based Computer Systems, Henry M. Levy, 1984. Paper 26: Architecture support for single address space operating systems, Eric J. Koldinger, Jeffrey S. Chase, and Susan J. Eggers, SIGPLAN Not. 27:175-186, September 1992 link.
Tuesday, May 7	Slippage	TBA
Thursday, May 9	Specialized architectures	Paper 15: Anton, a special-purpose machine for molecular dynamics simulation, David E. Shaw, Martin M. Deneroff, Ron O. Dror, Jeffrey S. Kuskin, Richard H. Larson, John K. Salmon, Cliff Young, Brannon Batson, Kevin J. Bowers, Jack C. Chao, Michael P. Eastwood, Joseph Gagliardo, J. P. Grossman, C. Richard Ho, Douglas J. Ierardi, Istvan Kolossvary, John L. Klepeis, Timothy Layman, Christine McLeavey, Mark A. Moraes, Rolf Mueller, Edward C. Priest, Yibing Shan, Jochen Spengler, Michael Theobald, Brian Towles, and Stanley C. Wang, SIGARCH Comput. Archit. News 35:1-12, June 2007 link. Paper 16: CryptoManiac: a fast flexible architecture for secure communication, Lisa Wu, Chris Weaver, and Todd Austin, ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, New York, NY, USA, 2001, pages 110-119 link. Additional readings if you are interested: Evaluating the Imagine Stream Architecture, Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, and Abhishek Das, ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture, Washington, DC, USA, 2004, page 14. Imagine: media processing with streams, B. Khailany, W.J. Dally, U.J. Kapasi, P. Mattson, J. Namkoong, J.D. Owens, B. Towles, A. Chang, and S. Rixner, Micro, IEEE 21(2):35-46, Mar/Apr 2001 link.
Tuesday, May 14	Program analysis	PAper 17: Automatically characterizing large scale program behavior, Timothy Sherwood, , Erez Perelman, , Greg Hamerly, , and Brad Calder, , ASPLOS-X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, New York, NY, USA, 2002, pages 45-57 link. Paper 18: Limits of control flow on parallelism, Monica S. Lam and Robert P. Wilson, SIGARCH Comput. Archit. News 20(2):46-57, 1992 link. Additional readings if you are interested: Phase tracking and prediction, Timothy Sherwood, Suleyman Sair, and Brad Calder, SIGARCH Comput. Archit. News 31(2):336-349, 2003 link. The intrinsic bandwidth requirements of ordinary programs, Andrew S. Huang and John Paul Shen, ASPLOS-VII: Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, New York, NY, USA, 1996, pages 105-114 link. Limits on multiple instruction issue, M. D. Smith, , M. Johnson, , and M. A. Horowitz, , SIGARCH Comput. Archit. News 17(2):290-302, 1989 link. Limits of instruction-level parallelism, David W. Wall, , ASPLOS-IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, New York, NY, USA, 1991, pages 176-188 link.
Thursday, May 16	New Technologies	Paper 19: An energy efficient cache design using spin torque transfer (STT) RAM, Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, and Sudhakar Yalamanchili, Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, New York, NY, USA, 2010, pages 389-394 link. Paper 21: Architecting phase change memory as a scalable dram alternative, Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger, SIGARCH Comput. Archit. News 37:2-13, June 2009 link.
Tuesday, May 21	Slippage	TBA
Thursday, May 23	No class	TBA
Tuesday, May 28	Power	Paper 23: Energy Optimization of Subthreshold-Voltage Sensor Network Processors, Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd Austin, and David Blaauw, ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture, Washington, DC, USA, 2005, pages 197-207 link. Paper 24: Temperature-aware microarchitecture: Modeling and implementation, Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang, Sivakumar Velusamy, and David Tarjan, ACM Trans. Archit. Code Optim. 1(1):94-125, 2004 link.
Thursday, May 30	Storage	Paper 13: A case for redundant arrays of inexpensive disks (RAID), David A. Patterson, Garth Gibson, and Randy H. Katz, Proceedings of the 1988 ACM SIGMOD international conference on Management of data, New York, NY, USA, 1988, pages 109-116 link. Paper 14: The case for RAMClouds: scalable high-performance storage entirely in DRAM, John Ousterhout, Parag Agrawal, David Erickson, Christos Kozyrakis, Jacob Leverich, David Mazieres, Subhasish Mitra, Aravind Narayanan, Guru Parulkar, Mendel Rosenblum, Stephen M. Rumble, Eric Stratmann, and Ryan Stutsman, SIGOPS Oper. Syst. Rev. 43:92-105, January 2010 link.
Tuesday, June 4	Programability	Paper 28: RCDC: a relaxed consistency deterministic computer, Joseph Devietti, Jacob Nelson, Tom Bergan, Luis Ceze, and Dan Grossman, SIGPLAN Not. 46:67-78, March 2011 link. Paper 27: Transactional Memory Coherence and Consistency, Lance Hammond, Vicky Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, and Kunle Olukotun, Proceedings of the 31st annual international symposium on Computer architecture, Washington, DC, USA, 2004, pages 102-- link.
Thursday, June 6	Potporri	Paper 29: Decoupled access/execute computer architectures, James E. Smith, , ACM Trans. Comput. Syst. 2(4):289-308, 1984 link. Paper 30: http://www.anandtech.com/show/4313/intel-announces-first-22nm-3d-trigate-transistors-shipping-in-2h-2011 http://www.intel.com/technology/silicon/integrated_cmos.htm http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04519636

Integrity Policy

Cheating WILL be taken seriously. Doing otherwise is not fair to honest students. It is also not fair to allow the cheater to thing that it is a reasonable alternative in life.
Please review the UCSD student handbook for more details on Academic Integrity.
Anyone copying information or having information copied during a test will receive an F for the class and will not be allowed to drop. They will be reported to their college dean. If you can prove non-cooperative copying took place, your grade may be restored, but you must prove it to the dean--I don't want to be involved. Anyone caught cheating or falsely representing the work of others on the homework will not be allowed to turn in further homework. Your grade will be based exclusively on the tests with a penalty of 25% OR GREATER applied.
We photocopy a random sampling of the exams in order to ensure that students do not modify their tests after they have been returned.
Online solutions, etc.: A solutions manual exists for this text. Using it, or any solutions you may find on the internet elsewhere IS CHEATING and will be dealt with accordingly. We know what the solution manual solutions look like. Homework is a small fraction of your grade.

Homework

Assignment 1: Administrivia
Assignment 2: Paper Reviews
Assignment 3: Class presentations