CSE141L Lab 2, Part A: Processor Front-End - Fetch Datapath

Lab Overview:

Lab Deliverables:

• Demonstration: None
• Progress Report: Answer all the questions that are found in the lab description. There are 7 total questions but they are much more involved than the questions in lab 1. Please read the "Important Note" section to see how you should name the PDF report. You will submit your progress report via the class moodle page.
• Files: You will need to submit all your Verilog (i.e. .v files). All of the Verilog files should be put into a single zip file that follows the naming convention described below. You will submit this zip file (along with your progress report) via the class moodle page.
  Important Note: In order to make sure none of your files are lost, you must follow these guidelines:
  1. All your Verilog files should have your name and student id in comments at the top.
  2. Your zip file should have the following naming convention: cse141L-lab2-part_a-lastname-firstname.zip. For example, Sat Garcia's zip file would have the following name: cse141L-lab2-part_a-Garcia-Sat.zip.
  3. Your progress report should be in PDF format and have the following naming convention: cse141L-lab2-part_a-lastname-firstname.pdf. For example, Sat's progress report would have the following name: cse141L-lab2-part_a-Garcia-Sat.pdf.

Lab Description:

Lab Files:

svn checkout svn://parallel.ucsd.edu/fetch-unit-datapath/trunk

Fetch Unit Specification

module fetch#(parameter I_WIDTH = 17, A_WIDTH = 10, O_WIDTH = 5)
(
	input	clk,

	// inputs from the exec unit
	input	dequeue_i,
	input	restart_i,
	input	[A_WIDTH-1 : 0]	restart_addr_i,

	// memory interface
	input	load_store_valid_i,
	input	store_en_i, 
	input	[A_WIDTH-1 : 0] load_store_addr_i,    
	input	[I_WIDTH-1 : 0]  store_data_i,        
	output	[I_WIDTH-1 : 0]  load_data_o,
	output	load_data_valid_o,

	// ouputs to the exec unit    
	output	[I_WIDTH-1 : 0]	instruction_data_o,
	output	[A_WIDTH-1 : 0]	instruction_addr_o,
	output	instruction_valid_o
);

1. An instruction contains 17 bits.
   • The most significant bit (MSB) is the 'P' (or "prediction") bit. If the 'P' bit is set to '0' then the instruction is either: a) not a branch or b) is a branch that has been predicted as 'not taken.'
   • The 5 least significant bits (LSBs) of the instruction are the 'offset' bits for branch instructions. We will use these 'offset' bits to calculate the branch target according to the following formula: target = PC + SignExt(offset). SignExt(offset) is simply the sign extended version of the offset. Note: The offset is given in 2's complement and therefore may contain a negative number. You do not have to worry about the other 11 bits of the instruction for this lab.
2. SRAM has 1024 (i.e. 1K) addresses and therefore uses 10 bits for addressing. Each address contains 17 bits of data. The implementation of the SRAM (ram17_1024.v) was created using MegaWizard, a utility from Altera, and is highly optimized. Please read the description of the file above to learn about what each address is initialized to in the SRAM.
3. The FIFO queue has 16 entries, each holding 27 bits of data. The entries of the FIFO are broken into two parts: 1) the address (10 bits) and 2) the instruction (17 bits).
4. In order to allow the program counter (PC) to restart at an arbitrary address, restart_i and restart_addr_i are provided as inputs to the fetch unit. If restart_i is set to '1' then the PC will change to the address specified by and the FIFO will be cleared. Using this mechanism, we can reset the fetch unit by setting restart_i to '1' and setting restart_addr_i to '0x0.' This will cause the fetch unit to start fetching instructions at address '0'.
5. To allow reading and writing to the SRAM, the fetch unit supports "load" and "store" instructions. Two inputs to the fetch unit, load_store_valid_i and store_en_i, fully specify load and store instructions. When load_store_valid_i is set to '1', the fetch unit knows the instruction is a load or store. Setting store_en_i to '1' further specifies the instruction as a store (conversely, a '0' value on store_en_i implies a load). For load instructions, the fetch unit produces a 17-bit instruction on the load_data_o output. In the case of a store, the fetch unit writes store_data_i into the address specified by store_addr_i.

1. In the absence of extenuating circumstance (e.g., fifo queue full, restart, or load/store), the fetch unit should fetch one instruction per cycle. Thus, it is a pipelined implementation,that is, it is computing the address of the next instruction at the same time that it is reading out the current instruction from the SRAM, and enqueing onto the FIFO.
2. Load and store instructions have a higher priority than fetching instructions, and should interrupt fetching for only one cycle. These memory operations receive higher priority because the processor back-end may be dependent on their timely execution. Also, the load/store signals are only a one cycle pulse and would be lost if they are not immediately serviced.
3. Restart signals only require a one cycle pulse of the restart signals. Thus, like for load/stores, it is important to make sure that your circuit does not "lose" the signal, even if other things like loads/stores are also asserted.

Datapath Implementation

The situation described in Q1 requires the use of an adder and MUX. Implement both of these components in Verilog in their respective files (adder.v and mux.v). Make sure you use RTL Verilog.

As mentioned earlier, the calculating the branch target requires the sign extended version of the offset. Implement the sign extension module in signext.v so that branches can function correctly. Hint: You can duplicate a bit N times by {N{1'bx}} in verilog. For example, 5'b11111 can be briefly expressed by {5{1'b1}}. )

You should now be ready to implement your fetch unit in Verilog (fetch.v). In doing so, you should follow these simple guidelines:

1. Use structural verilog, not a behavioral verilog or RTL verilog. You should instantiate mux, adder, and signext modules in the fetch.v file. The FIFO and RAM have already been instantiated in fetch.v for you..
2. Use always_ff and non-blocking assignments (i.e. <=) for registers.
3. Where applicable, always use signal names in the provided datapath schematic. Otherwise, use consistent and readable naming style. The naming convention, proper indentation, and style will be graded. Make sure your Verilog file is readable in the Quartus II editor.
4. Your Verilog modules should be both synthesizable and implementable in Quartus II.
5. You may want to peek ahead to Q7 to understand structures in SystemVerilog.

SystemVerilog Practice

Good luck!