cse240c: Advanced Microarchitecture

WLH 2110
Lectures Tue. & Thu., 3:30-4:50
Spring, 2010
Shortcuts: Schedule Homeworks

Instructor

Steven Swanson

Email:

swanson

cs.ucsd.edu

IM (not email): professorswanson@{AIM, Yahoo!, google talk, MS Messenger}
Office: EBU3B 3212
Office Hours: By appointment
UCSD homepage

Course Description

This course will cover advanced topics in processor microarchitecture. We will cover both the "latest and greatest" as well as the "oldies but goodies" in both commercial processors and architecture research. We will learn answers to questions like:

What are {super,multi,data,synchro,chrono,wave}scalar and why is everyone always talking about them?
How many pipeline stages does it to take to melt a pentium?
What do natural selection and branch prediction have to do with each other?
How do you design a processor to fit into your eyeball without cooking your brain?

The basic format for the class will be: Read papers and discuss. There will also be a mid-sized project.

Text books

Required: Assigned readings throughout the quarter. See the schedule below

Grading

Note that 50% of you grade is determined by preparing for and participating in class.

Paper summaries	33%	You will summarize each paper we read in class. Summaries are due 20 minutes before class begins. No exceptions. This means there is no reason to be late for class to complete your summary.
Class participation	33%	This class is discussion driven, so must come prepared to discuss the material. This includes showing up. You should contribute to the discussion very nearly every day.
In class presentations	33%	In lieue of exams, each of you prepare and present two presentations on topics we will cover.

Schedule

Items in the schedule more that one week in the future are subject to change. Check back for updates for the assigned readings, etc. Deadlines for homeworks/projecsts that have been assigned be not be moved earlier.

I will post the slides for the lectures once I receive them from the presenter.

Date	Topic	Readings	Slides	Due	Notes
Tuesday, March 30	Administrivia.		00_Introduction.pdf
Thursday, April 1	Historical perspectives	Architecture of the IBM System/360, G. M. Amdahl, G. A. Blaauw, and Jr. F. P. Brooks, :17-31, 2000 link. Parallel operation in the control data 6600, James E. Thornton, :5-12, 1995 link. Additional readings if you are interested: Design of a Computer -- The Control Data 6600, James E. Thornton, link. Considerations in Computer Design - Leading up to the Control Data 6600, James E. Thornton, , 1963 link. IBM's 360 and early 370 systems, Emerson Pugh, Lyle R. Johnson, and John H. Palmer MIT Press, 1991.	presentation1_dhcurran.pdf, presentation1withAnswers_dhcurran.pdf		David Curran
Tuesday, April 6	Historical perspectives	Cramming More Components Onto Integrated Circuits, G.E. Moore, Proceedings of the IEEE 86(1):82-85, Jan 1998 link. The history of the microcomputer-invention and evolution, S. Mazor, Proceedings of the IEEE 83(12):1601-1608, Dec 1995 link. Additional readings if you are interested: A 4096-bit dynamic MOS RAM, J. Karp, W. Regitz, and S. Chou, Solid-State Circuits Conference. Digest of Technical Papers. 1972 IEEE International XV: 10-11, Feb 1972 link. A three transistor-cell, 1024-bit, 500 NS MOS RAM, W. Regitz and J. Karp, Solid-State Circuits Conference. Digest of Technical Papers. 1970 IEEE International XIII: 42-43, Feb 1970 link. Design of ion-implanted MOSFET's with very small physical dimensions, R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous, and A.R. LeBlanc, Solid-State Circuits, IEEE Journal of 9(5): 256-268, Oct 1974 link. The future of wires, R. Ho, K.W. Mai, and M.A. Horowitz, Proceedings of the IEEE 89(4):490-504, Apr 2001 link. A whole issue of IEEE Solid-State Circuits Society News about Dennardian Scaling. link.	MooreMazor-1.ppt.pdf	Assignment 1;	S.N. Hemanth Meenakshisundaram presents
Thursday, April 8	Historical perspectives	The CRAY-1 computer system, Richard M. Russell, Commun. ACM 21(1):63-72, 1978 link. Tarantula: a vector extension to the alpha architecture, R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec, Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on:281-292, 2002 link. Additional readings if you are interested: An analysis of the Cray-1 computer, Richard L. Sites, ISCA '78: Proceedings of the 5th annual symposium on Computer architecture, New York, NY, USA, 1978, pages 101-106 link.			Jorgen Tjerno Presents
Tuesday, April 13	No Class
Thursday, April 15	Catch up	TBA
Tuesday, April 20	Unconventional OOO exeuction	Monsoon: an explicit token-store architecture, G.M. Papadopoulos and D.E. Culler, Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on:82-91, May 1990 link. Executing a program on the MIT tagged-token dataflow architecture , Arvind and R.S. Nikhil, Computers, IEEE Transactions on 39(3):300-318, Mar 1990 link. Additional readings if you are interested: Critical issues regarding HPS, a high performance microarchitecture, Y. N. Patt, S. W. Melvin, W. M. Hwu, and M. C. Shebanow, SIGMICRO Newsl. 16(4):109-116, 1985 link. First version of a data flow procedure language, J. B. Dennis, Programming Symposium, Proceedings Colloque sur la Programmation, London, UK, 1974, pages 362-376.
Thursday, April 22	Unconventional OOO exeuction	Area-Performance Trade-offs in Tiled Dataflow Architectures Swanson, S., Putnam, A., Mercaldi, M., Michelson, K., Petersen, A., Schwerin, A., Oskin, M., and Eggers, S. J. SIGARCH Comput. Archit. News 34, 2 (May. 2006), 314-326. link Tartan: evaluating spatial computation for whole program execution, Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish Venkataramani, Seth C. Goldstein, and Mihai Budiu, ASPLOS-XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems, New York, NY, USA, 2006, pages 163-174 link. Additional readings if you are interested: The WaveScalar architecture, Steven Swanson, Andrew Schwerin, Martha Mercaldi, Andrew Petersen, Andrew Putnam, Ken Michelson, Mark Oskin, and Susan J. Eggers, ACM Trans. Comput. Syst. 25(2):4, 2007 link. Focus on Section 1-4, and skim the rest. . Spatial computation, Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein, ASPLOS-XI: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems, New York, NY, USA, 2004, pages 14-26 link. NanoFabrics: spatial computing using molecular electronics, Seth Copen Goldstein and Mihai Budiu, ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, New York, NY, USA, 2001, pages 178-191 link.			Jorgen Tjerno Presents
Tuesday, April 27		TBA
Thursday, April 29	Unconventional OOO exeuction	Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D.C. Burger, S.W. Keckler, and C.R. Moore. 2003 International Symposium on Computer Architecture (ISCA), June, 2003. link Composable Lightweight Processors, Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, and Stephen W. Keckler, MICRO '07: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC, USA, 2007, pages 381-394 link. Additional readings if you are interested: Universal Mechanisms for Data-Parallel Architectures, Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, and Doug Burger, MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC, USA, 2003, page 303 link. A design space evaluation of grid processor architectures, R. Nagarajan, K. Sankaralingam, D. Burger, and S.W. Keckler, Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International Symposium on: 40-51, Dec. 2001 link.			Ryan Gabrys
Tuesday, May 4	Reliability	Transient fault detection via simultaneous multithreading, Steven K. Reinhardt and Shubhendu S. Mukherjee, SIGARCH Comput. Archit. News 28(2):25-36, 2000 link. DIVA: a reliable substrate for deep submicron microarchitecture design, Todd M. Austin, MICRO 32: Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, Washington, DC, USA, 1999, pages 196-207 link. Additional readings if you are interested: A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor, Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steven K. Reinhardt, and Todd Austin, MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC, USA, 2003, page 29 link.
Thursday, May 6	Slippage	TBA
Tuesday, May 11	Circuit-level microarchitectural issues	ReCycle:: pipeline adaptation to tolerate process variation, Abhishek Tiwari, Smruti R. Sarangi, and Josep Torrellas, ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture, New York, NY, USA, 2007, pages 323-334 link. Razor: a low-power pipeline based on circuit-level timing speculation, D. Ernst, Nam Sung Kim, S. Das, S. Pant, R. Rao, Toan Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on: 7-18, Dec. 2003 link.			Gautham Presents
Thursday, May 13	Circuit-level microarchitectural issues	The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays, M. S. Hrishikesh, Doug Burger, Norman P. Jouppi, Stephen W. Keckler, Keith I. Farkas, and Premkishore Shivakumar, SIGARCH Comput. Archit. News 30(2):14-24, 2002 link. Optimum Power/Performance Pipeline Depth, A. Hartstein and Thomas R. Puzak, MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC, USA, 2003, page 117 link.			Gautham Presents
Tuesday, May 18	No class	TBA
Thursday, May 20	Data analysis	TBA
Tuesday, May 25	Specialized architectures	Imagine: media processing with streams, B. Khailany, W.J. Dally, U.J. Kapasi, P. Mattson, J. Namkoong, J.D. Owens, B. Towles, A. Chang, and S. Rixner, Micro, IEEE 21(2):35-46, Mar/Apr 2001 link. CryptoManiac: a fast flexible architecture for secure communication, Lisa Wu, Chris Weaver, and Todd Austin, ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, New York, NY, USA, 2001, pages 110-119 link. Additional readings if you are interested: Evaluating the Imagine Stream Architecture, Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, and Abhishek Das, ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture, Washington, DC, USA, 2004, page 14.			Hemanth Presents
Thursday, May 27	Program analysis	Automatically characterizing large scale program behavior, Timothy Sherwood, , Erez Perelman, , Greg Hamerly, , and Brad Calder, , ASPLOS-X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, New York, NY, USA, 2002, pages 45-57 link. Limits of control flow on parallelism, Monica S. Lam and Robert P. Wilson, SIGARCH Comput. Archit. News 20(2):46-57, 1992 link. Additional readings if you are interested: Phase tracking and prediction, Timothy Sherwood, Suleyman Sair, and Brad Calder, SIGARCH Comput. Archit. News 31(2):336-349, 2003 link. The intrinsic bandwidth requirements of ordinary programs, Andrew S. Huang and John Paul Shen, ASPLOS-VII: Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, New York, NY, USA, 1996, pages 105-114 link. Limits on multiple instruction issue, M. D. Smith, , M. Johnson, , and M. A. Horowitz, , SIGARCH Comput. Archit. News 17(2):290-302, 1989 link. Limits of instruction-level parallelism, David W. Wall, , ASPLOS-IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, New York, NY, USA, 1991, pages 176-188 link.			Ryan Gabrys
Tuesday, June 1	Case studies	Case study: Nehalem Itanium Processor Microarchitecture, Harsh Sharangpani, and Ken Arora, , IEEE Micro 20(5):24-43, 2000 link. EPIC: Explicitly Parallel Instruction Computing, M.S. Schlansker and B.R. Rau, Computer 33(2):37-45, Feb 2000 link. The microarchitecture of the pentium 4 processor, Dave Sager, Desktop Platforms Group, and Intel Corp, Intel Technology Journal 1:2001, 2001 link. The Alpha 21264 microprocessor architecture, R.E. Kessler, E.J. McLellan, and D.A. Webb, Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on:90-95, Oct 1998 link.			David Presents
Thursday, June 3	Power	Energy Optimization of Subthreshold-Voltage Sensor Network Processors, Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd Austin, and David Blaauw, ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture, Washington, DC, USA, 2005, pages 197-207 link. Temperature-aware microarchitecture: Modeling and implementation, Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang, Sivakumar Velusamy, and David Tarjan, ACM Trans. Archit. Code Optim. 1(1):94-125, 2004 link.			David Presents

Integrity Policy

Cheating WILL be taken seriously. Doing otherwise is not fair to honest students. It is also not fair to allow the cheater to thing that it is a reasonable alternative in life.
Please review the UCSD student handbook for more details on Academic Integrity.
Anyone copying information or having information copied during a test will receive an F for the class and will not be allowed to drop. They will be reported to their college dean. If you can prove non-cooperative copying took place, your grade may be restored, but you must prove it to the dean--I don't want to be involved. Anyone caught cheating or falsely representing the work of others on the homework will not be allowed to turn in further homework. Your grade will be based exclusively on the tests with a penalty of 25% OR GREATER applied.
We photocopy a random sampling of the exams in order to ensure that students do not modify their tests after they have been returned.
Online solutions, etc.: A solutions manual exists for this text. Using it, or any solutions you may find on the internet elsewhere IS CHEATING and will be dealt with accordingly. We know what the solution manual solutions look like. Homework is a small fraction of your grade.

Homework

Assignment 1: Discussion board and grading administrivia
Assignment 2: Paper Summaries
Assignment 3: Class presentations