`timescale 1ns / 1ps

/*
 * CSE141L Lab1: Tools of the Trade
 * University of California, San Diego
 * 
 * Written by Matt DeVuyst, 3/30/2010
 */

module test_adder#(parameter W = 8);

   reg          clk;
   reg  [W-1:0] inA;
   reg  [W-1:0] inB;
   wire [W-1:0] out;
   wire         isOdd;

   // The design under test is our adder
   adder dut (clk, inA, inB, out, isOdd);

   // Toggle the clock every 10 ns
   initial
     begin
        clk = 0;
        forever #10 clk = !clk;
     end

   // Test with a variety of inputs.
   // Introduce new stimulus on the falling clock edge so that values
   // will be on the input wires in plenty of time to be read by
   // registers on the subsequent rising clock edge.
   initial
     begin
        inA = 0;
        inB = 0;
        #20;
        inA = 1;
        inB = 1;
        #20;
        inA = 5;
        inB = 6;
        #20;
        inA = 2;
        inB = 2;
        #20;
        inA = 3;
        inA = 3;
        #20;
        inA = 1;
        inB = 8;
     end // initial begin

endmodule // test_adder