CSE 141L: Introduction to Computer Architecture Lab

Instructor

Michael B. Taylor
	email
EBU 3B 4110	office
	gchat

Teaching Assistant

Arash Arfaee
	email

Class Meetings

	Date	Time	Location
Lecture	F	2:00p-3:20p	EBU 3B 2154

Join and monitor this google group immediately:
cse-141-lab-taylor

Office Hours

Prof	Michael Taylor
where	(via gchat)
when	anytime; will respond when available often good times: TuTh 7-9a & 5-6p

TA	Arash Arfaee
when	Tuesday and Thursday 3:00-4:00PM
where	EBU3 260B

Course Description

From this course, you will:

Learn correct hardware design practices suitable for FPGA and VLSI digital design.

Learn how to write Synthesizable Verilog, and use the tools to turn it into a circuit.

Design, Implement and Test your own processor, although way to an FPGA bitstream.

Learn about computer architecture in the best way -- by doing.

Work in a team, building a large, complex system using design principles that apply to both software and hardware.

Help your classmates and exercise your creativity.

This course is taught in tandem with CSE 141. Unless you have discussed it with me, you should be enrolled in both.

Grading

There are two ways to get an "A" in this class. One is to implement a working processor by the end of the quarter that executes the selected programs in an ISA of your design. This is the grading option you should strive for; however even for the strongest student, there is always the change you will be unlucky.

The other way is to do well on the labs and class participation. If your processor doesn't turn out as well, I will consider your performance on the labs and participation (see below). Your grade will be at least the maximum of the "your processor works" grade and the lab assignment grade.

In addition to the labs, you should be an active contributer to the google group. The tools are challenging and sometimes buggy. Your classmates (in addition to the course's staff) are an excellent resource for help with the tools.

This class is about doing. You will learn almost everything you learn in this class by doing it. This means that you (or your team) must do all your own work. As long as you meet this criteria, you can consult with and discuss your project with other groups. We have structured the course so that there is no incentive to be stingy with your knowledge of the tools or in sharing your expertise with your classmates.

Labs	86%	They are equally weighted.
Class Participation	14%	Being an active and positive influence in class or on the Google Group.

START YOUR LABS AS SOON AS THEY ARE HANDED OUT.

Late turn ins For many of you, this project will be the most complex thing you have ever designed. Each of the labs uses the results of the last, so you cannot simply skip a lab. Worse, each lab seems hard, but seems easy in comparison to the next. If you are late on one lab, then it will have a cascading effect on future labs, and you will run out of time at the end of the class. In order to encourage this, we will offer "limited amnesty" for late labs, which means that the penalty applied to your grade is a function of time. The slope of the amnesty curve is set after the lab is turned in, and can be as high as 15% per day.

Tool Problems Tool problems are part of the hardware design process. You should expect to have unexpected delays. To the extent that it is a fundamental issue with the tools that requires real resolution by the TA, we will be more understanding if 1) you posted the issue to the Google Group, 2) show clear evidence that you actively tried to solve the problem yourself and 3) it was clear you started early on the lab.

Grading Appeal Process If you feel there has been an error in how an assignment was graded, you have one week from when the assignment is return to bring it to our attention. You must submit to the appropriate TA a written description of the problem issue, what you feel the fair resolution is, and your unmodified coursework. We photocopy a random sampling of student work to detect inappropriate modifications. Note that we regrade the entire hw; so your grade may either rise or fall after resubmission. Should, after you appeal, you be unsatisfied with the TA's treatment of the issue, you may resubmit the appeal to the professor.

Schedule

NOTE: Subject to skew and jitter. We reserve the right to change this. I will post the slides for most lectures. Since the slides contain material I am not allowed to distribute publicly, they are only available from on campus or via the campus proxy. Instructions for setting up the proxy can be found here. Using the proxy is useful in general, since it gives you full access to the libraries and other resources from off campus.

Fri, April 02	Lab 1; Introduction; Verilog		slides
Fri, April 09	Lab 2a; Verilog; Fetch Units	Lab 1 Due	slides
Fri, April 16	Lab 2b; Fetch Units; Testing	Lab 2A Due
Fri, April 23
Fri, April 30	Lab 3A;	Lab 2B Due (May 2/3/4; 0/3/5 penalty)
Fri, May 07	Lab 3B;	Lab 3A Due May 10
Fri, May 14		Lab 3B Drop 1 Due May 17
Fri, May 21	Lab 4;	Lab 3B Final Due May 24
Fri, May 28
Fri, June 04	Pizza Party; Prizes	Lab 4 Due

Teaming

Starting with Lab 3A, you will be working in a team of two people. If you are a strong student, it is OK to work solo. I highly recommend against taking another major project class at the same time as 141L.

Pick your partner wisely, and show your partner that you are a good candidate by doing well in the Labs 1, 2A, and 2B. It's perfectly reasonable to ask what their grade was on the assignment before agreeing to partner with them. You may also want to talk about what your expectations for how aggressive a project you want to do.

If you have already taken CSE 141 in the past, and thus are not currently enrolled, then you should start looking for a partner immediately, because it may be harder for you to find one.

You are not allowed to join a team unless you have completed Labs 1, 2A, and 2B. It's not fair to the other members if you do not have the basic knowledge to design hardware.

You may not switch team members. However, in extreme cases, you may elect to leave the group; you should talk to the professor and TA in this case. In that case, each student continues the project individually.

Academic Integrity

Cheating is unacceptable. Our policy in this class is to aggressively pursue cheaters, and to ensure that they receive the maximum penalty allowable under the University of California academic system. If you are choosing between turning in an assignment late, or using somebody's else work, do yourself a favor and just turn it in late. You are facing a permanent mark on your academic record and a certainty of having to explain it to any future employer or school that you apply to.

Initial Labs For the initial labs, you will work alone. You may posted code to the Google Group to demonstrate a question or an answer, but you may not post any part of your assignment that you plan to turn in.

Project For the labs, if they are group labs, you may obviously work with your group members. With non-group members, you may brainstorm about your design but you better make sure there are substantial differences between what you and they are doing, and you must write your own code. We will use automatic software for finding inappropriate similarities between student code, and substantial similarities in student designs (including to previous teachings of the class) could result in us requiring the student to redo the assignment. In cases of code copying, we will refer the student to UCSD for cheating.