CSE141L Lab 3, Part 1: Designing an ISA - How To Talk To Your CPU

Lab Overview:

Lab Description:

A Letter to the AwesomeCore, Inc CEO

Re: New AwesomeCore Processor Design

Dear Cob,

As you might have heard, Lenti and AND are both planning on making a major announcement at the end of June. Our analysts have indicated that they are likely to be announcing powerful new CPUs that could further strengthen their grip on the processor design market. The business strategist at Orerson Consulting says that if we are to have any hope of succeeding with our next processor design, it needs to come out quickly. Futhermore, our other competitor, Moon, Inc., is too well established in the area of MIPS/SPARC design for us to be able to rely on designing our next CPU around that. We need to come up with a unique design that will create some excitment among our potential customers. By making it unique enough, we can also patent many aspects of the design so no one will be able to encroach on our slice of the market.

We are hoping that you can pull together a team that can provide us with a new instruction set architecture that looks novel enough that we will have ample material to patent. We suggest as a start that you use a 17-bit fixed instruction size and 34-bit word size; that combination may help you explore a new design space. Furthermore, Moon has access to the MIPS and SPARC patent portfolio, so try not to be too similar to them. Of course, our products still need to be competitive, so the ISA should be general purpose and reasonably efficient. Also, since the fuse is relatively short on this, you will need to keep it simple. Your compensation will be based on the correctness, novelty and efficiency of the end product. But most importantly, you must deliver a preliminary ISA by May 2 (1.5 weeks), the validated ISA by May 6 (0.5 weeks), and a final FPGA prototype by May 27 (3 weeks).

Thanks in advance,
Jake

ISA Goals:

1. General Purpose - Your processor should be able to execute all of the given benchmark programs as well as other general programs.
2. Novelty - Your ISA should not be a clone of an existing ISA (such as MIPS or SPARC). While there will obviously need to be some overlap with these other ISAs, the overlap should be minimized.
3. Performance - Programs should execute reasonably quickly on your processor.

ISA Requirements:

• Instruction Width: 17 bits
• Word Size: 34 bits
• Include the following 2 instructions:
  • in [dest] [channel[3:0]] - Read 34 bits of data from the specified channel and save at [dest].
  • out [src] [channel[3:0]] - Write 34 bits of data from [src] to the specified channel.
  See the section on Input/Output Instruction below for more details on these instructions.
• Extra opcode space must be reserved to allow for extra instructions to be added later.
• Of course, it must be general purpose enough to run the benchmarks and other general programs.

Input/Output Instructions:

I/O instructions have blocking semantics. If there is no data available to read by the in instruction, the processor simply waits until there is available data. Similarly, upon an out instruction, the processor must wait until the write operation completes; it might need to wait for available buffer space. You can freely use channels for various purposes such as debugging and multicore interface.

Benchmark Programs:

For the following benchmarks, you should assume that all data and address pointers are 34-bit.

Program Loader

// function loader:
//    load a program in the data memory into the specified address of
//    the instruction memory
// 
// src:  source address of the program in the data memory
// dest: destination address of the program in the instruction memory
// size: number of instructions to load, assume an even number
// part0(dptr *src):return 17-bit of the 34-bit data at src
// part1(dptr *src):return the remaining 17-bit of the 34-bit data at src
//
// note: this program does not need to run fast; but it does need to run. 
//       dptr means data pointer which points to a 34-bit data, 
//       while iptr means instruction pointer which points to a 17-bit instruction. 
//       Since a data is 34-bit and an instruction is 17-bit, one data location contains 
//       two instructions; part0 and part1 returns one of the two instructions, respectively.

void loader(dptr *src, iptr *dest, int size)
{
    int i
    for (i = 0; i < size; i+=2)
    {
        *dest++ = part0(src);
        *dest++ = part1(src);
        src++;
    }
    return;
}

Virtual Machine

// function virtualmachine:
//    emulates the execution of a very simple ISA
// 
// opcodes
// 0: subtract
// 1: right shift
// 2: nor
// 3: swap
// 4: in
// 5: out
// 6: conditional jump with link
// 7: halt
//
// note: int is 34 bits

struct inst {
	int op;
	int srcA;
	int srcB;
	int dest;
};

int VirtualMachine(int pc, int *mem)
{
	while(1)
	{
		struct inst *instruction = mem[pc];
		int op = instruction->op;
		int srcA = instruction->srcA;
		int srcB = instruction->srcB;
		int dest = instruction->dest;
		pc = pc + 4;
						    
		switch(op) {
			case 0: mem[dest] = mem[srcA] - mem[srcB]; break;
			case 1: mem[dest] = mem[srcA] >> 1; break;
			case 2: mem[dest] = ~(mem[srcA] | mem[srcB]); break;
			case 3: temp = mem[srcB]; mem[dest] = mem[mem[srcA]]; mem[mem[srcA]] = temp; break;
			case 4: in  mem[dest], mem[srcA]; break; // in  mem, channel #
			case 5: out mem[srcA], mem[srcB]; break; // out data, channel#
			case 6:
				mem[dest] = pc;
				if (mem[srcA] < 0) pc = mem[srcB];
				break;
			case 7: return pc;
		}
	}
}

Fibonacci Number

// Recursive Fibonacci
//  get 'n'th fibonacci number
// You should not alter the algorithm

int fib(int n)
{
	if (n < 0)
		return 0x3DEADBEEF;
	else if (n <= 2)
		return 1;
	else if (n == 29)
		return 514229;
	else if (n == 30)
		return 832030;
	else if (n == 48)
		return 4807526976;
	else if (n == 49)
		return 7778742049;
	else return fib(n-1) + fib(n-2);
}

Feasibility of Place & Route

Useful Resources