| From: | Jake Ivring; | CTO | UnicationITY, Inc. | ||
| To: | Cob Bolwell; | Principle | FlexGermanica Technical, LLC. |
Dear Cob,
Our revenues are getting hit by the knock-off clones from our low-cost rival, Boatorola Corp. The business strategist from Underson Consulting says our only hope for survival is to patent every aspect of our product. However, since many of the components are standard, there is nothing to patent. We need to redesign each piece so that it explores non-standard parts of the design space, which being new, will give our patent attorneys fodder for patent filings. Then when Boatorola copies us, we litigate for patent infringement!
We are hoping that you can pull together a team that can provide us with a new instruction set architecture that looks novel enough that we will have ample material to patent. We suggest as a start that you use a 17-bit fixed instruction size and 34-bit word size; that combination may help you explore a new design space. Furthermore, Boatorola has access to the MIPS and SPARC patent portfolio, so try not to be too similar to them. Of course, our products still need to be competitive, so the ISA should be general purpose and reasonably efficient. Also, since the fuse is relatively short on this, you will need to keep it simple. Your compensation will be based on the correctness, novelty and efficiency of the end product. But most importantly, you must deliver a preliminary ISA by May 2 (1 week), the validated ISA by May 9 (1 week), and a final FPGA prototype by May 30 (3 weeks).
Thanks in advance,
Jake
You can work in a team of two, and it is highly recommended. However, if your team mate drops this class, you must finish the project alone. So pick your partner wisely. Alternatively, you may work alone. Moderately higher standards are expected for teams of two over teams of one.
You should declare your team by the following steps:
Ultimately your ISA and resulting implementation will be evaluated according to the following criteria:
Your ISA should fulfill the following requirements.
I/O instructions have blocking semantics. If there is no data available to read by the in instruction, the processor simply waits until there is available data. Similarly, upon an out instruction, the processor must wait until the write operation completes; it might need to wait for available buffer space. You can freely use channels for various purposes such as debugging and multicore interface.
Three benchmarks are provided to help guide your ISA development. In lab 2a, you will write assembly programs based on your ISA for all three benchmarks. Assume that all the addresses (pointers) and data in the benchmark programs are 34 bit.
// function loader:
// load a program in the data memory into the specified address of
// the instruction memory
//
// src: source address of the program in the data memory
// dest: destination address of the program in the instruction memory
// size: number of instructions to load, assume an even number
// part0(dptr *src):return 17-bit of the 34-bit data at src
// part1(dptr *src):return the remaining 17-bit of the 34-bit data at src
//
// note: this program does not need to run fast; but it does need to run.
// dptr means data pointer which points to a 34-bit data,
// while iptr means instruction pointer which points to a 17-bit instruction.
// Since a data is 34-bit and an instruction is 17-bit, one data location contains
// two instructions; part0 and part1 returns one of the two instructions, respectively.
void loader(dptr *src, iptr *dest, int size)
{
int i
for (i = 0; i < size; i+=2)
{
*dest++ = part0(src);
*dest++ = part1(src);
src++;
}
return;
}
// function supergarbage:
// perform various operations
//
// opcodes
// 0: subtract
// 1: right shift
// 2: nor
// 3: swap
// 4: in
// 5: out
// 6: conditional jump with link
// 7: halt
//
// note: int is 34 bits
struct inst {
int op;
int srcA;
int srcB;
int dest;
};
int SuperGarbage(int pc, int *mem)
{
while(1)
{
struct inst *instruction = mem[pc];
int op = instruction->op;
int srcA = instruction->srcA;
int srcB = instruction->srcB;
int dest = instruction->dest;
pc = pc + 4;
switch(op) {
case 0: mem[dest] = mem[srcA] - mem[srcB]; break;
case 1: mem[dest] = mem[srcA] >> 1; break;
case 2: mem[dest] = ~(mem[srcA] | mem[srcB]); break;
case 3: temp = mem[srcB]; mem[dest] = mem[mem[srcA]]; mem[mem[srcA]] = temp; break;
case 4: in mem[dest], mem[srcA]; break; // in mem, channel #
case 5: out mem[srcA], mem[srcB]; break; // out data, channel#
case 6:
mem[dest] = pc;
if (mem[srcA] < 0)
{
pc = mem[srcB];
}
break;
case 7: return pc;
}
}
}
// Recursive Fibonacci
// get 'n'th fibonacci number
// You should not alter the algorithm
int fib(int n)
{
if (n < 0)
return 0x3DEADBEEF;
else if (n <= 2)
return 1;
else if (n == 29)
return 514229;
else if (n == 30)
return 832030;
else if (n == 48)
return 4807526976;
else if (n == 49)
return 7778742049;
else return fib(n-1) + fib(n-2);
}
In lab 3, you will be implementing your ISA in a Xilinx FPGA. If you are unfamiliar with these, please skim a Xilinx manual.
Note that one of the important aspects of your design is that it needs to fit within the subset of Xilinx parts that the Xilinx ISE WebPACK can synthesize to. The list of parts is given at: http://www.xilinx.com/ise/devsys_feature_guide.pdf. We recommend you target the XC4VLX25.
You can look for the Xilinx product tables
to get a rough idea of how big a design these parts can hold. A logic cell is roughly equivalent to a gate. In any event, you should keep your design to well under 10,000 flip flops, and under 15,000 logic gates. So, for instance, a 32-element 16-bit register file is likely to have at least 32x16 = 512 flip-flops, and probably at least one gate per flip flop to control it. The instruction and data memories will be mapped to separate block-rams which are available on the Xilinx part. These will be between 2 and 100 kilobytes, however you should not assume anything about their size. Make sure your ISA design can support an instruction and data address space of the full 34-bit range. Overly small address spaces is the #1 reason ISA's fail! Multipliers are fairly big, but the latest Xilinx parts include on-chip multipliers, which are fair game, but possibly unnecessary. Some Xilinx parts have on-board PowerPC processors; you should not assume these will be available to you.
Of course, you want your ISA to be portable to future Xilinx generations (and indeed, it is not clear which Xilinx part we will be able to run your design on at the end of the class), so we recommend against optimizing your design too much for any one Xilinx part.