LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.all;
USE  IEEE.STD_LOGIC_ARITH.all;
USE  IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY GrayCounter IS
PORT(	clock, pb1, pb2		: IN std_logic;
		seg_a1, seg_b1, seg_c1, seg_d1, seg_e1, 
		seg_f1, seg_g1, dp1	: OUT std_logic;
		seg_a2, seg_b2, seg_c2, seg_d2, seg_e2,
		seg_f2, seg_g2, dp2	: OUT std_logic;
		code_out			: OUT std_logic_vector(3 DOWNTO 0)
	);
END GrayCounter;

ARCHITECTURE Moore OF GrayCounter IS
	TYPE STATE_TYPE IS (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P);

	attribute syn_encoding : string;
	attribute syn_encoding of STATE_TYPE : type is "gray"; 	-- Change the encoding scheme here
	
	SIGNAL state						: STATE_TYPE;
	SIGNAL pb12							: std_logic_vector(1 DOWNTO 0);
	SIGNAL ctrl_clock, slow_clock		: std_logic;
	SIGNAL code							: std_logic_vector(3 DOWNTO 0);

COMPONENT CLK_DIV
PORT(	
	clock_25Mhz				: IN	STD_LOGIC;
	clock_1MHz				: OUT	STD_LOGIC;
	clock_100KHz			: OUT	STD_LOGIC;
	clock_10KHz				: OUT	STD_LOGIC;
	clock_1KHz				: OUT	STD_LOGIC;
	clock_100Hz				: OUT	STD_LOGIC;
	clock_10Hz				: OUT	STD_LOGIC;
	clock_1Hz				: OUT	STD_LOGIC);
END COMPONENT;

-- Define your display component here

BEGIN

clk1: CLK_DIV
port map( clock_25Mhz => clock, clock_1Hz => ctrl_clock);


-- invoke your display component here

	PROCESS (ctrl_clock)
	BEGIN

		pb12 <= pb1 & pb2;
						
		IF ctrl_clock'EVENT AND ctrl_clock = '1' THEN
			-- Case statement to determine next state
			-- This is what you want to edit. We have left you two states to 
			-- get started. The rest you must figure out. 
			CASE state IS
				WHEN A =>
					CASE pb12 IS
						WHEN "01" => state <= B; -- Up
						WHEN "00" => state <= P; -- Down
						WHEN OTHERS => state <= A;
					END CASE;
				
				WHEN B =>
					CASE pb12 IS
						WHEN "01" => state <= C; -- Up
						WHEN "00" => state <= A; -- Down
						WHEN OTHERS => state <= B;
					END CASE;
				
				-- Complete the remaining state transitions here
				
			END CASE;
		END IF;
	END PROCESS;

	-- Outputs that depend on state

	WITH state SELECT
		code	<=	"0000"	WHEN A,
					"0001"	WHEN B,
					
					-- Complete the remaining output here
					
	code_out <= code;

	-- Outputs that do not depend on states
		dp1 <= '1';
		seg_a2 <= '1';
		seg_b2 <= '1';
		seg_c2 <= '1';
		seg_d2 <= '1';
		seg_e2 <= '1';
		seg_f2 <= '1';
		seg_g2 <= '1';
		dp2 <= '1';
		
END Moore;