|
Objective
In this lab, we will build a simple system using datapath, memory, registers, control
logic and a program counter. We use buses and standard modules as basic building blocks for datapath, memory, registers and program counter design, and use VHDL code for control subsystem.
Note that in this lab, we use FPGA Family: Virtex2, Device Type: XC2V80-5CS144.
The Project
Design a simple system that can perform addition, shift, comparison, and
masking. The system reads a 8-bit value from the read-only memory (ROM) block (3-bit instruction set &
5-bit data). The memory block should be able to hold at least 16 instructions. There are three 5-bit registers R1, R2, and R3. Registers R1 and R2
store the data. Register R3 presents the result of the calculations. There
are also a 1-bit flag for overflow and another 1-bit flag for comparison. We list the specification of the
instructions:
|
Command
|
3-bit Inst.
|
5-bit Data
|
Description
|
|
1 Init
|
000
|
XXXXX
|
Initialize all registers, ie R1=R2=R3=(0,0,0,0,0)
|
|
2 Move1
|
001
|
aaaaa
|
Put aaaaa value into register R1
|
|
3 Move2
|
010
|
bbbbb
|
Put bbbbb value into register R2
|
|
4 Store
|
011
|
XXXXX
|
Take the previous result in R3 and store into register R2
|
|
5 Add
|
100
|
XXXXX
|
Add contents in R1 and R2. Present the result at R3 and output overflow flag
|
|
6 Shift
|
101
|
aaXXX
|
Left shift the content in R2 by aa bits (no rotate), then store the result in R3
|
|
7 Comp
|
110
|
XXXXX
|
Compare the contents of R1 and R2. The flag bit is false if R2 > R1.
|
|
8 Mask
|
111
|
XXXXX
|
Mask (AND-ing) R1 and R2. Present the result in R3
|
*For 5-bit data, X is Don't Care.
**Note that register R1 holds its
content except for instructions 1 and 2. Register R2 holds except for
instructions 1, 3, and 4. Register R3 holds except for instructions 1, 5, 6, 8.
In addition, a program counter and control subsystem are needed to make the whole system works.
Report
Title page:
- Names
of students and due date.
- Title
of the lab and objective.
- A brief
description of each person's contribution.
Contents:
- Schematic diagrams of the top-level design, memory, datapath, registers and program counter - must use bus.
- VHDL code of the control subsystem using one truth table.
- Layout of the design (FPGA)
- Your instructions in the memory
- Functional simulation of your instructions . Demonstrate the content of the output of each of the 8 instructions. Label and explain the data before and
after each operation.
- Discussion of the verification. Show the reason why we are confident that the
system can function properly. List the process needed for the proof.
- Illustrate the worst delay path between registers with timing simulation.
Grading
90% will be based on the completeness and
correctness of the report.
10% will be based on the neatness, organization, and following instruction of
the report format.
|