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Objective
In this lab, we will design a pattern recognizer. We first use the state diagram to specify the system as a finite state machine. We then use VHDL for the implementation. We will try different state assignments, use Mealy and Moore machines, and compare the results.
Note that in this lab, we use FPGA Family: Virtex2, Device Type: XC2V80-5CS144.
Part 1. The Finite State Machine
The finite state machine is a pattern recognizer, which has a one-bit input, x, and a one-bit output, z. Whenever the input string x(t, t-4) matches the pattern "11011" or "11001", the machine outputs a '1' for one clock cycle. Otherwise, the output is '0'. Overlaps of the patterns are allowed.
Part 2. Mealy Machine
Implement the pattern recognizer as a Mealy machine. Try three different codings for state assignments. (hint: Use a state diagram to specify the machine. Convert the specification to a VHDL program. Edit the program and synthesize the machine as a macro cell.)
Given an input sequence x= "11101110011010", display the timing diagrams of the three implementations. (hint: Initialize the state to start the simulation)
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Change the input sequence to demonstrate the glitch of the Mealy machine. ( 5 percent bonus if you show how to eliminate the identified glitch)
Part 3. Moore Machine
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Implement the pattern recognizer as a Moore machine. Use three different codings for state assignments.
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Given the same input sequence as in Part 1.ii, display the timing diagrams of the three implementations.
- Demonstrate an input sequence (if any) that causes a glitch in the Moore machine.
Part 4. Comparison
Use a table to compare the six different implementations (three different state assignments for both Mealy and Moore machines), in terms of the number of states, number of flip-flops, number of lines of VHDL codes, and the number of Configurable Logic Blocks (CLBs: boxes in layout).
Report
Title page:
- Names
of students and due date.
- Title
of the lab and objective.
- A brief
description of each person's contribution.
Contents:
Part 1: A summary for the design and implementation process
in the lab with less than 80 words.
Part 2: i. the state diagram, three VHDL programs (The first VHDL code should be complete. The other two showing the difference from the first), and three
FPGA layout figures. ii. three timing diagrams. iii. the timing diagram, and a short explanation why the glitch happens.
Part 3: i. the state diagram, three VHDL programs, and three
FPGA layout figures. ii. three timing diagrams, iii. the timing diagram showing the glitch, or an explanation why there is no glitch.
Part 4: The comparison table.
Grading
90% will be based on the completeness and
correctness of the report.
10% will be based on the neatness, organization, and following instruction of
the report format.
You will get 5 percent bonus if you show how to eliminate the glitch you identified for the mealy machine in Part 2. |