CSE 140L Hardware Lab Two,
Spring 2005, CK Cheng

The Specification and Usage of Flip-Flops

Due time: Right before class on May 4

Objective

In this lab, we learn the specification and usage of flip-flops. We design and implement a serial to parallel shift register, three different counters, and a pseudo-random sequencer.

Note that in the lab, we use FPGA Family: Virtex2, Device Type: XC2V80-5CS144.

Part 1. Serial to Parallel Shift Register

Build a 4-bit serial to parallel shift register using four FDCEs.

  1. Design and implement the circuit.
  2. Verify the correctness of the design. Show exactly 8 clock cycles of behavior simulation result.
  3. Observe the critical path, and demostrate the critical path by timing simulation.

Part 2. Asynchronous Counter

Build a 4-bit asynchronous counter using four FTCEs and invertors.

  1. Design and implement the circuit.
  2. Verify the correctness of the design. Show exactly 18 clock cycles of timing simulation result.
  3. Build a 8-bit asynchronous counter, and create a test bench as follow: Clock High/Low Time: 6ns; Input Setup Time: 4ns; Output Valid Delay 1ns; CLR is valid untill 110ns; Simulation End Time: 520ns. Simulate the test bench and mark the time point where the counter fails, explain why it fails.

Part 3. Synchronous Counter

Build a 4-bit synchronous counter using four FDCEs and combinational gates.

  1. Design and implement the circuit.
  2. Verify the correctness of the design. Show exactly 16 clock cycles of behavior simulation result.
  3. Observe the critical path, and demostrate the critical path by timing simulation.

Part 4. Gray Counter

Build a 4-bit Gray Counter using four FTCEs and combinational gates.Design and implement the circuit.

  1. Design and implement the circuit.
  2. Verify the correctness of the design. Show exactly 16 clock cycles of behavior simulation result.
  3. Observe the critical path, and demostrate the critical path by timing simulation.

Part 5. Pseudo Random Sequencer

Build a 4-bit Pseudo Random Sequencer using four FDPEs and one XOR gate. The initial value is "1111".

  1. Design and implement the circuit.
  2. Verify the correctness of the design. Show exactly 16 clock cycles of behavior simulation result.
  3. Observe the critical path, and demostrate the critical path by timing simulation.

Report

Title page:

  • Names of students and due date.
  • Title of the lab and objective.
  • A brief description of each person's contribution.

Content:

  • Part 1 i (schematic diagram), ii (behavior simulation diagram),
    iii (timing report, post-place&route simulation diagram).
  • Part 2 i (schematic diagram), ii (behavior simulation diagram),
    iii (schematic diagram, post-place&route simulation diagram, explanation).
  • Part 3 i (schematic diagram), ii (behavior simulation diagram),
    iii (timing report, post-place&route simulation diagram).
  • Part 4 i (schematic diagram), ii (behavior simulation diagram),
    iii (timing report, post-place&route simulation diagram).
  • Part 5 i (schematic diagram), ii (behavior simulation diagram),
    iii (timing report, post-place&route simulation diagram).
  • Use a table to list the advantages and disadvantages of the three counters in parts 2-4.

Grading

90% will be based on the completeness and correctness of the report.
10% will be based on the neatness, organization, and following instruction of the report format.