Objective
In this lab, we learn the specification and usage of flip-flops.
We design and implement a serial to parallel shift register, four different counters,
and a pseudo-random sequencer.
Note that in the lab. we use FPGA Family: Spartan2, Device Type: xc2s30-5tq144.
Part 1. Serial to Parallel Shift Register
Build a 3-bit serial to parallel shift register using three FDCEs.
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i.
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Design and implement the circuit.
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ii.
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Build and simulate the circuit using Xilinx.
Show exactly 8 clock cycles of timing simulation result.
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Part 2. Asynchronous Counter
Build a 4-bit asynchronous counter using four FTCEs.
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i.
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Design and implement the circuit.
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ii.
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Build and simulate the circuit using Xilinx.
Show 18 cycles of timing simulation result.
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iii.
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Increase the length of the counter to demonstrate a case
that the counter fails, explain why it fails, and formulate
the conditions when it fails.
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Part 3. Synchronous Counter
Build a 4-bit synchronous counter using four FTCEs and combinational gates.
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i.
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Design and implement the circuit.
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ii.
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Build and simulate the circuit using Xilinx.
Show exactly 16 cycles of timing simulation result.
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Part 4. Johnson Counter
Build a 4-bit Johnson Counter using four FDCEs.
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i.
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Design and implement the circuit.
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ii.
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Build and simulate the circuit using Xilinx.
Show at least 12 clock cycles of data.
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Part 5. Odd Length Walking-Ring Counter
Build a 4-bit Odd Length Walking-Ring Counter using four FJKCEs.
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i.
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Design and implement the circuit.
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ii.
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Build and simulate the circuit using Xilinx.
Show at least 8 clock cycles of data.
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Part 6. Pseudo Random Sequencer
Build a 4-bit Pseudo Random Sequencer using four FDCEs and combinational gates.
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i.
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Design and implement the circuit.
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ii.
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Build and simulate the circuit using Xilinx.
Show at least 17 clock cycles of data.
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Report
Title page:
- Names of students and due date.
- Title of the lab and objective.
- A brief description of each person's contribution.
Content:
- Part 1 i (schematic diagram), ii (timing diagram).
- Part 2 i (schematic diagram), ii (timing diagram), iii (timing diagram).
- Part 3 i (schematic diagram), ii (timing diagram).
- Part 4 i (schematic diagram), ii (timing diagram).
- Part 5 i (schematic diagram), ii (timing diagram).
- Part 6 i (schematic diagram), ii (timing diagram).
- Use a table to list the advantages and disadvantages of the four counters in parts 2-5.
Grading
90% will based on the completeness and correctness of the report. 10% will
based on the neatness, organization, and following instruction of the report
format.
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