Tutorial for Lab 1

Step-by-Step Instructions for Building a Full Adder in Xilinx

  1. Open up Xilinx Project Navigator
    1. Under Windows XP, go to Start->All Programs->Xilinx ISE 4->Project Navigator
    2. Click on File->New Project
      1. Type in a Name (ie Full Adder)
      2. Select in Spartan2 for Device Family
      3. Select in xc2s30-5tq144 for Device
      4. Select XST VHDL for Design Flow.
  2. Add Schematic for Half Adder
    1. We will be building a Full Adder out of two Half Adders. The logic for a Half Adder is as follows:
      Truth Table for Half Adder
      A
      B
      S
      Co
      0
      0
      0
      0
      0
      1
      1
      0
      1
      0
      1
      0
      1
      1
      0
      1

      The logic turns out to be: S = A xor B; Co = AB

    2. Create the Schematic for the Half Adder
      1. Go to Project->New Source
      2. Select 'Schematic' and give a filename (ie half_adder)

      3. After clicking OK, the Schematic Editor will start.
      4. Click on the Add Symbol button ( ) and the Symbol Side Bar should appear.
      5. Select an XOR2 gate by finding it in the side bar and clicking once on it.
        1. Move your mouse on to the canvas area and see how the item you selected is dragged along with it.
        2. Click once again to place it on the canvas
      6. Do the same again for an AND2 gate
      7. Now select the wiring tool ()
      8. Draw the appropriate wire connections between the gates and leave excess wire for input and output connections.


      9. Now select the Add I/O Marker tool ()
      10. Select the option that says "Input" and then click near the two wires on the left hand side of the drawing.
      11. Next select the option that says "Output" and click near the two wires on the right hand side of the schematic.
      12. After you have drawn all the IO Connectors, now double click on each of them and give them appropriate names (ie. A, B, S, Co).


      13. Now we have to make this a symbol in itself so that we can use it to build the Full Adder.
        1. Click on Tools->Create Symbol
        2. Make sure that the inputs and outputs are correctly labeled and hit OK

    3. Create the Full Adder
      1. Close down the HA schematic
      2. Create a new schematic by going to Project->Add Source and selecting schematic and naming it full_adder.
      3. When the new schematic editor opens and you click on the Symbol Tool (), you should see your Half_Adder symbol that you just created.
      4. Click on that and bring two instances of it on to your drawing.
      5. The truth table for a Full Adder is as follows:

        Truth Table for Full Adder
        A
        B
        Ci
        S
        Co
        0
        0
        0
        0
        0
        0
        0
        1
        1
        0
        0
        1
        0
        1
        0
        0
        1
        1
        0
        1
        1
        0
        0
        1
        0
        1
        0
        1
        0
        1
        1
        1
        0
        0
        1
        1
        1
        1
        1
        1

      6. Now to complete the Full Adder, you just have to wire the inputs and outputs correctly, add the appropriate IO Connectors and then simulate to make sure it is right.

      7. Always save the schematic before you simulate.
      8. To print out your schematic, go to File->Print Setup and choose the appropriate paper size (8.5x11) and then go to File->Print and it should print out for you.
  3. Simulation
    1. The first thing you have to do before you can simulate is to create a Test Bench. Back at the Project Navigator, select Project->New Source and select Test Bench Waveform.
    2. Give it a name (ie. full_adder_tbw) and hit OK


    3. Hit OK on the next popup as well... allowing the default values:


    4. Next, a window will pop up with all of your signals (inputs and outputs).
    5. By clicking on the lines of your input signals at different times, it will change the value of that particular signal. Making sure that you go through all the possible combinations for inputs, your window should look close to the following:


    6. Hit Save and then another window will popup asking how many cycles to continue the simulation. Select 5 and then hit OK. Close the window.
    7. Back at the Project Navigator window, make sure you have the Test Bench Waveform file that you just created selected, or click on it to select it.
      1. In the option pane below that, now select Generate Expected Simulation Results (double click on it)


      2. This will open another window that looks similar to the previous window you had open, except that the output (hopefully correct) values will be visible.
      3. Make sure that the values are correct, otherwise go back and make sure your schematics have been properly implemented.
      4. Close the window after the signals have been verified.
    8. Now go back to the Project Navigator and to get the most accurate timing simulation, double-click on the Simulate Post-Place & Route VHDL Model
    9. This will produce a series of windows and you might have to zoom out to see the entire waveform.


    10. You will notice that when an input changes (ie. A->0/1) and all the other inputs are 0, that the S signal goes to 1, but only after a short delay. You will also see that there are small pieces of the signal that jump to the opposite value and almost immediately jump back to their original value; these are due to glitches in the system (you don't have to worry about them right now).

If you have any questions or get stuck in this tutorial, please email Chris at croedel@cs