Time: TuTh 5:00-6:20, Place: AP&M 4882
Instructor: Dean Tullsen
Office Hours: by appt.
Background (for those who haven't read it already)
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, and R.L. Stamm,In 23rd Annual International Symposium on Computer Architecture, May, 1996
Actual papers to be discussed:
Execution-based
Prediction Using Speculative Slices
Craig B. Zilles and Gurindar S. Sohi
28th International Symposium on Computer Architecture (ISCA-28), 2000.
Speculative Precomputation: Long-range Prefetching of Delinquent Loads, Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery, John P. Shen, In 28th International Symposium on Computer Architecture, July, 2001
April 8: Hardware Support for SP (Jeff Brown)
Dynamic Speculative Precomputation, Jamison D. Collins, Dean M. Tullsen, Hong Wang, John P. Shen, In 34th Annual International Symposium on Microarchitecture, December, 2001
Speculative Data-Driven Multithreading, Amir Roth and G. S. Sohi, Seventh International Symposium on High-Performance Computer Architecture (HPCA-7), Jan. 2001.
April 10: SP-based architectures (Rakesh Kumar)
(optional background paper)
Multiscalar Processors, G. S. Sohi, S. Breach, and T. N. Vijaykumar, 22th International Symposium on Computer Architecture, 1995.
(actual papers)
Master/Slave Speculative Parallelization, Craig Zilles (University of Illinois) and Guri Sohi (University of Wisconsin) ISCA 2002
Z. Purser, K. Sundaramoorthy, and E. Rotenberg. "A Study of Slipstream Processors". 33rd International Symposium on Microarchitecture, December 2000
April 15: Speculative Multithreading (Weifeng Zhang)
Speculative Multithreaded Processors, G. S. Sohi and Amir Roth, IEEE Computer, vol. 34, no. 4, April 2001
J.G. Steffan and T.C. Mowry. "The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization." In Proc. HPCA-4, pp. 2–13, 1998
April 17: Speculative Multithreading II (Satish Narayanasamy)
"A
Quantitative Assessment of Thread-Level Speculation Techniques"
Pedro Marcuello and Antonio González, Proc. of the 1st. Int.
Parallel and Distributed Processing Symposium (IPDPS'00), Cancún
(Mexico), May 1-4 2000
A Dynamic Multithreading Processor, H. Akkary and M. Driscoll, 31st International Symposium on Microarchitecture, Nov 1998
April 22: SMT Compilation (Yuanfang Hu)
Design and Evaluation
of Compiler Algorithms for Pre-Execution
Dongkeun Kim, Donald Yeung, ASPLOS 2002
Compiling
for Instruction Cache Performance on a Multithreaded Architecture
Rakesh Kumar and Dean M. Tullsen (University of California, San Diego)
April 24: Custom hardware ISAs (Wei Chuang)
The
MAJC Architecture: A Synthesis of Parallelism and Scalability
Marc Tremblay, Jeffrey Chan, Shailender Chaudhry,
Andrew W. Conigliaro, Shing Sheung Tse,IEEE Micro, vol.20,
no.6, Nov.-Dec. 2000, pp.12-25.
The
Microarchitecture of the Pentium® 4 Processor
Glenn Hinton, Dave Sager, Mike Upton, Darrell Boggs, Doug Carmean,
Alan Kyker, Patrice Roussel,
April 29: custom ISAs (Michael Van Biesbrouck)
The
Technology Behind Crusoe Processors
By: Alexander Klaiber
D. H. Friendly, S. J. Patel, and Y. N. Patt, "Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors", Proceedings of MICRO-31, 1998, pp. 173-181
May 1: custom ISAs (Nathan Tuck)
Yuan Chou, Pazhani Pillai, Herman Schmit, and John Paul Shen "PipeRench Implementation of the Instruction Path Coprocessor" presented at MICRO '00.
Kemal Ebcioglu and Erik R. Altman, DAISY: Dynamic Compilation for 100% Architectural Compatibility, ISCA 24
Achieving High Performance via Co-Designed Virtual Machines, J. E. Smith, S. Sastry, T. Heil, T. Bezenek, International Workshop on Innovative Architecture, Maui High Performance Computer Center, Oct. 26-28, 1998.
Exploiting
ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu
Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore, University
of Texas at Austin
Dynamic
Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture
Greg Semeraro, David H. Albonesi, Steven G. Dropsho, Grigorios Magklis,
Sandhya Dwarkadas, and Michael L. Scott (University of Rochester)
Seshan N. High VelociTI processing Texas Instruments VLIW DSP architecture. IEEE Signal Processing Magazine, vol.15, no.2, March 1998, pp.86-101. (one commercial architecture. Figures aren't all readable -- do the best you can.)
Efficient
use of memory bandwidth to improve network processor throughput
Jahangir Hasan, Satish Chandra, and T. N. Vijaykumar
To appear in Proceedings of the 30th Annual International Symposium
on Computer Architecture (ISCA), June 2003
Mark Oskin, Justin Hensley, Diana Keen, Matthew Farrens, Frederic T. Chong, Aneet Chopra. Exploiting ILP in Page-Based Intelligent Memory. 1999 International Symposium on Microarchitecture (MICRO32)
Detailed
Design and Evaluation of Redundant Multithreading Alternatives. S.
S. Mukherjee, M. Kontz, and S. K. Reinhardt. Proc. 29th Annual Int'l Symp.
on Computer Architecture (ISCA), pp. 99-110, May 2002
Martyn Amos, Paul E. Dunne, and Alan Gibbons. Efficient
time and volume DNA simulation of CREW PRAM algorithms.
Technical Report CTAG-98006, Department of
Computer Science, University of Liverpool, UK,
May 1998
Unscheduled Papers
Characterizing and Predicting Value Degree of Use
J. Adam Butts and Gurindar S. Sohi (University of Wisconsin)
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective
Replay
Dan Ernst, Andrew Hamel, and Todd Austin, University of Michigan
Half-price Architecture
Ilhyun Kim, and Mikko H. Lipasti, UW-Madison
Runahead Execution: An Alternative to Very Large Instruction Windows
for Out-of-order Processors
Onur Mutlu, Jared Stark,
Chris Wilkerson, and Yale Patt
Tradeoffs in Buffering Memory State for Thread-Level Speculation in
Multiprocessors
Maria Garzaran, Milos Prvulovic,
Victor Vinals, Jose Llaberia,
Lawrence Rauchwerger, and
Josep Torrellas
Enhancing Software Reliability with Speculative Threads
Jeffrey Oplinger, Monica S. Lam
Pointer-Cache Assisted Prefetching, Jamison Collins, Suleyman Sair,
Brad Calder, and Dean Tullsen, In 35th Annual International Symposium on
Microarchitecture, November 2002.
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput
Jahangir Hasan, Purdue University; Satish Chandra, IBM India Research
Lab; T. N. Vijaykumar, Purdue University
Imagine: Media Processing with Streams
Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, Peter
Mattson, Jinyung Namkoong, John D. Owens, Brian Towles, and Andrew Chang
IEEE Micro, March/April 2001, pp. 35-46.
Saving and Restoring Implementation Contexts with co-Designed Virtual
Machines, A. Dhodapkar, J. E. Smith, Workshop on Complexity Effective Design,
Gothenburg, Sweden, June 30, 2001.
The Jrpm System for Dynamically Parallelizing Java Programs
Michael Chen, and Kunle Olukotun, Stanford University