Final Project Due June 7th

From the high level design in assignment #5 you will implement the accelerator in Verilog and use Synopsys to evaluate the design timing, area and power. The accelerator will be tuned and its design will be optimized to achieve reasonable timing, area and power results. These metrics will then be combined with SimpleScalar simulation results to compare a processor with your custom accelerator to one without.

A final write up of the architecture, accelerator and performance results will be turned in, along with the Verilog implementation of the accelerator. The writeup needs to include the performance of the application, the application's important places to optimize, the architecture of the accelerator, the methodology used, and performance results. The final write up should also include figures and graphs to help describe and understand the accelerator and its performance.

What to turn in:

• The relevant source code again, highlighting what part is removed due to the their hardware acceleration.
• Turn in your Verilog diagram/architectural schematic, timing diagram, and area report. The architectural schematic should describe how the hardware accelerator interacts with your core ARM processor. From the synthesis of your Verilog design you will determine the latch to latch delay in ns of the critical path through their design. You need to make sure that the timing results make sense (a reasonable critical path is found).
• You need to calculate performance using ARM SimpleScalar (a different simulator and ISA is OK if it has been approved by us, but it needs to be a performance simulator). Performance needs to be calculated using XScale as the baseline processor for a 300 MHZ and 1GHZ design (a configuration file is provided with ARM simulator). You will convert ns delay calculated in prior bullet to cycles in the baseline processor to model how long it takes to execute a call to the accelerator. You need to report the CPI, data cache miss rates, branch miss rates, and number of cycles with and without the accelerator, as well provide the percent speedup achieved using the accelerator.
• Finally, answer the following questions about your design:
  • How did your design change from planning to implementation to testing?
  • What is the critical path of your accelerator?
  • How is the data communication to and from your accelerator handled in your design? How much does this affect the performance of using the accelerator?
  • If you had more time, what would you change about your accelerator design?
  • Do you think that other code loops from your program or other programs could map easily down to an accelerator similar to yours? If so which one's and why (briefly), and if not how could you extend your design so that it could be used by other programs (briefly)?
• Email the original source program you optimized to calder@cs, along with the inputs and how to run it. Make sure that you highlight with comments the section/area you optimized. If you changed the code, email the optimized code as well.