The application performance analysis done in the prior assignment will have pinpointed the important parts of the application. These are the parts to optimize with a custom accelerator. As part of this assignment, you will turn in the high level design of your accelerator as well as a performance estimate of how much gain your accelerator could gain.
Before building the accelerator in hardware (Verilog), it is important to first provide an analysis of the potential benefits of your optimization. For example, the performance estimation should be done in Simplescalar assuming you can perform your accelerated hardware in N cycles. This provides a rough estimation as to the benefits of your accelerator and is used to help tune and guide the development of your accelerator.
In order to perform this analysis in SimpleScalar, you would need to modify your program or simulator to replace the instructions that would be executed in the accelerator to take only Y cycles of latency, instead of N in the baseline architecture, where Y should be less than N. Comparing the execution time of these two runs of the program provides the estimated performance improvement. This can be performed similar to what you did in assignment #2 to find out the percent of cycles spent executing a specific procedure, especially if you break the code to be accelerated out into its own procedure.