// Verilog behavioral description of a 32-bit adder
module process_32_bit_adder(addend_one, addend_two, carry_in, sum, carry_out);
   input [31:0] addend_one;
   input [31:0] addend_two;
   input carry_in;
   output [31:0] sum;
   output carry_out;

   reg [31:0] sum;    // Declare as type reg since assigned to in the always block.
   reg carry_out;
   reg [32:0] carry;
   integer i;

   always@(addend_one or addend_two or carry_in)    // sensitivity list
   begin: add_32_bit_process
   carry[0] = carry_in;
   for (i=0;i<=31; i=i+1)  
      begin
      sum[i] = addend_one[i] ^ addend_two[i] ^ carry[i];
      carry[i+1] = addend_one[i] & addend_two[i] | 
                   addend_one[i] & carry[i] |
                   addend_two[i] & carry[i];
      end
   carry_out = carry[32];
   end
endmodule