CSE 241 -- Advanced Computer Architecture

Spring 2002, Instructor: Dean Tullsen

Announcements:

Lecture slides posted. See below.
Homework 1 posted.

Homework assignments

Basic Course Information:

Instructor: Dean Tullsen

AP&M 4250
office hours: M 3-4, Th 2:15-3:15

Meeting times

TuTh 12:45-2:05, McGill 1320 (WLH 2207 for first class)

Course textbook

Patterson & Hennessy, "Computer Architecture: A Quantitative Approach", Morgan Kaufmann, Second Edition
Hill, Jouppi, Sohi, "Readings in Computer Architecture", Morgan Kaufmann
these will be supplemented with other readings during the course. Stay tuned.

Other recommended reading

CPU Info Center

everything you'd ever want to know about available commercial CPUs

WWW Computer Architecture Home Page

a comprehensive guide to research and general information on computer architecture available on the web.

Assignments will be quite varied. Examples of things you may be asked to do in this class:

problem sets
paper summaries -- a paper summary is no more than 1 page long (no more than 2 pages total for all papers for a particular day), and contains the following information: (1) summary of the paper [in the neighborhood of 2-3 sentences, everything else about 1 sentence each], (2) What is the most important result?, (3) One strength of the paper, (4) one weakness of the paper, (5) one thing you didn't understand, (6) if you wrote this paper, what would your next paper be about?
mini-project -- this could be either an easy programming project or an easy simulation project.
project -- this is a unique piece of work, done in groups of 1-3, of high depth and quality.

Grades will be determined something like this:

homework, paper summaries, mini-projects 20%
project 30%
midterm 15%
final 25%
class participation 10%

Class will be a combination of lecture and guided discussion. Make sure you come prepared for the latter. If not, I will bump up the portion of the grade for class participation until I am happy with the level of discussion.
A class mailing list will be set up. Make sure you're on it.

Course Outline:

I. Parallel Computer Architecture

cache coherence protocols
synchronization
consistency models
case studies

II. Historical Architectures

III. Instruction Level Parallelism

branch prediction
ILP limits
predicated execution
dynamic scheduling
case studies

IV. Cache/Memory Hierarchy

V. I/O Architecture

VI. Other Interesting Architectures

dataflow machines
multithreading
trace processors
speculative threading

Lecture slides: L1, L2, L3

Class	Readings (Very approximate, at this point!)
April 2	Introduction
April 4	H&P 8.1-8.4
April 9	H&P 8.5, 8.6
April 11	H&P 8.7-8.11
April 16	The DASH Prototype: Logic Overhead and Performance.
April 18	Memory Coherence in Shared Virtual Memory Systems, An Evaluation of Software-Based Release Consistent Protocols
April 23	Architecture and Applications of the HEP multiprocessor computing system, The Tera Computer System, Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
April 25	Tera Hardware-Software Cooperation
April 30	(1)Architecture of the IBM System/360 (2) Parallel Operation in the Control Data 6600 (3) The CRAY-1 Computer System (4) CRAY-1 Computer Technology also read pages 1-16 of the text (pages 1-55 in total)
May 2	(1) Cramming More Components onto Integrated Circuits, (2) Two-Level Adaptive Training Branch Prediction
May 7	*midterm*
May 9	(1) Combining Branch Predictors (2) The YAGS branch prediction scheme (3) Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
May 14	(1) A Comparison of Full and Partial Predicated Execution Support for ILP Processors (2) Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors (3) Highly accurate data value prediction using hybrid predictors
May 16	(1) The Alpha 21264 Microprocessor (2) The Microarchitecture of the Pentium 4 Processor
May 21	(1) Improving Direct-Mapped Cache ... (Jouppi) (2) Organization and Performance of a Two-Level ... (Wang, Baer, Levy)
May 23	(1) Execution-based Prediction Using Speculative Slices (2) Dynamic Speculative Precomputation
May 28	(1) Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching (2) Putting the fill unit to work: dynamic optimizations for trace cache microprocessors
May 30	(1) Multiscalar Processors (2) Threaded Multi-path Execution
June 4	(1) Focusing Processor Policies via Critical-Path Prediction (2) Reducing Power with Dynamic Critical Path Information
June 6	Final
June 11	Project Presentations
June 13	Project Reports Due