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Objective
In this lab, we will build a full-adder, a 4-bit adder from the full-adder. Likewise, we will build a full-subtractor, and a 4-bit subtractor.
Moreover, we build a 2-input multiplexer, and a 4-input multiplexer.
We study the waveforms and the
delay of the logics. Use ONE worst case to demonstrate the timing diagram.
Note that in the lab. we use FPGA Family:
XC4000E, Part: 4003EPC84 and Speed: 1.
Part 1. Tutorial
Go through the
tutorial posted on http://www.prenhall.com/xilinx
(tutorials 1, 2, 5, 6, 10).
Write a summary of
the tutorials commenting on the process and how to aviod the possible mistakes in less than 40 words.
Part 2. Adders
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i.
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Use the enclosed full
adder tutorial to build a full adder using xilinx program. Simulate the
logic to verify the function. Use the timing diagram to demonstrate the
delay of the circuit. Mark the amount of the delay.
Print the physical layout of the circult.
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ii.
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Build a 4-bit adder using xilinx & simulate the
4-bit adder using xilinx. Use the timing diagram to demonstrate the worst delay
of the circuit. Mark the amount of the delay.
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Part 3. Subtractors
i.
Design a full-subtractor. Simulate the logic to verify the
function. Use the timing diagram to demonstrate the delay of the circuit.
Mark the amount of the delay.
ii.
Build a 4-bit subtractor. Use the timing diagram to demonstrate
the worst delay of the circuit. Mark the amount of the delay.
Part 4. Multiplexer
Build a circuit that translate a 4-bit parallel data to a serial output using
only 2:1 Muxes.
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i.
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Define the specification for this 4-bit parallel to
serial circuit. (input, output & their relationship)
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ii.
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Briefly describe how you design this circuit.
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iii.
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Build and simulate the circuit using xilinx. Use the timing
diagram to demonstrate the delay of the circuit. Mark the amount of the
delay.
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Report
Title page:
- Names of students and
due date.
- Title of the lab and
objective.
- A brief description of each
person's contribution.
Content:
- Part 1 summary of the
tutorials
- Part 2 i (timing diagram, FPGA layout), ii (timing diagram)
- Part 3 i (timing diagram), ii (timing diagram)
- Part 4 i, ii, iii (timing diagram)
- Hint on a good report:
Be descriptive but not wordy. Think of yourself as the grader but
doesn't have the hand out. The grader should know what you did in the
lab without looking at the hand out. **Also, remember to have a short
description on what test cases you used (preferably label the test cases
on the simulation print-out). Labeling 0's and 1's on your simulation
timing chart will also help the grader to identify which test cases you
have used.
Grading
90% will based on the completeness and correctness of the report. 10% will
based on the neatness, organization, and following instruction of the report
format.
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