homework solutions posted here.
midterm May 10, solutions.
Basic Course Information:
II. Historical Architectures
III. Instruction Level Parallelism
IV. Cache/Memory Hierarchy
V. I/O Architecture
VI. Other Interesting Architectures
| Class | Readings |
| April 3 | Introduction, Vijay Pai talk |
| April 5 | H&P 8.1-8.4, assignment 1 due April 12, slides |
| April 10 | H&P 8.5, 8.6, slides |
| April 12 | H&P 8.7-8.11, slides,assignment 2 due April 19 |
| April 17 | The DASH Prototype: Logic Overhead and Performance. |
| April 19 | |
| April 24 | Memory Coherence in Shared Virtual Memory Systems,
Is SC + ILP = RC? |
| April 26 | Architecture and Applications of the HEP multiprocessor computing system,
The Tera Computer System, Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor |
| May 1 | Tera Hardware-Software Cooperation |
| May 3 | (1)Architecture of the IBM System/360
(2) Parallel Operation in the Control Data 6600 (3) The CRAY-1 Computer System (4) CRAY-1 Computer Technology also read pages 1-16 of the text (pages 1-55 in total) |
| May 8 | (1) Cramming More Components onto Integrated Circtuits,
(2) Two-Level Adaptive Training Branch Prediction |
| May 10 | midterm |
| May 15 | (1) Combining
Branch Predictors
(2) The YAGS branch prediction scheme |
| May 17 | (1) A Comparison of Full and Partial Predicated Execution Support for
ILP Processors
(2) Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors (3) Highly accurate data value prediction using hybrid predictors |
| May 22 | (1) The
Alpha 21264 Microprocessor
(2) The MIPS R10000 Superscalar Microprocessor |
| May 24 | (1) Improving Direct-Mapped Cache ... (Jouppi)
(2) Organization and Performance of a Two-Level ... (Wang, Baer, Levy) |
| May 29 | Memorial Day Holiday |
| May 31 | (1) Trace
Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
(2) Putting the fill unit to work: dynamic optimizations for trace cache microprocessors (3) Trace Processors |
| June 5 | (1) Multiscalar
Processors
(2) Threaded Multi-path Execution |
| June 7 | Project Presentations |
If you have comments or suggestions, email me at tullsen@cs.ucsd.edu