I. Introduction (intro)
II. Performance (perf)
III. Instruction set architecture (isa)
IV. Pipelining (pipe1,pipe2,pipe3)
V. Instruction Level Parallelism (ilp1,ilp2,bp,ilp3)
VI. Memory (cache1,cache2)
If you have comments or suggestions, email me at tullsen@cs.ucsd.edu