CSE 30 -- Lecture 6 -- Oct 15

MIPS instruction . Page 118 of Patterson & Hennessey. Simple fixed size instructions permit easier (faster) decoding of the op-code, using less chip real-estate. There are thirty two general purpose 32-bit registers. There are two instruction encoding formats: one is for three-operand instructions, where all three operands are registers, and the other is for two and three operand instructions, where there are two fields for specifying registers and one 16-bit constant. (The lw instruction uses this and is a two operand instruction, and the addi also uses this but is usually considered a three operand instruction.)

Load-store architecture. Most instructions manipulate registers only. There are two special instructions lw (load word) and sw (store word) which transfer data between registers and memory.

An important reason why load/store architectures are preferred arises due to faults and interrupts. In class, we discussed page faults:

The operating system provides the virtual memory abstraction for application programs, just as it provides the filesystem abstraction. In the filesystem abstraction, the operating system hides the details of how to interact with the disk hardware from the application program, allowing the application program to be unaware of the type of disk hardware used. This means that an application program can be moved to a computer (using the same operating system) with different kinds of disk hardware, and the program will still work. Similarly, in the virtual memory abstraction the operating system hides the detail of how much real memory (aka physical memory, or DRAM) is available on the machine, allowing the application program to allocate memory (request memory from the OS) even beyond the amount actually available.

The way this works is by dividing memory into regions called pages -- typically of 4096 bytes each -- and employing a memory management unit (MMU) which translates virtual addresses, the addresses that the application program uses, into physical addresses, the addresses that the hardware uses. Thus, the OS is free to move the actual location of the contents of a virtual memory page around in physical memory, as long as it fixes the address translation done by the MMU so that the program can still access the memory.

In addition to simply moving the memory, the OS can remove memory pages from RAM by first writing it to the disk. If the program later tries to access that memory, a page fault occurs, where the program is suspended and the OS gains control of the processor. At ths point, the OS determines where the memory contents reside on disk, frees up a page of physical memory, and copies the on-disk copy back into physical memory. Then, the OS changes the address translation in the MMU so that the virtual-to-physical translation will work properly, and the application's instruction that caused the page fault is restarted or continued. The application is unaware that anything had happened -- it just runs a little slower.

Load/store architectures differ from older, CISC style architectures in that there are no complex addressing modes. An add instruction is simply

	add $r1,$r2,$r3
where the operands are registers. In a CISC architecture where complex addressing modes are available, it might look like
	add 4($r1)+$r2,24($r3)+$r4,4($r5)+$r6
which could be the simple, direct translation of C code:
	array1[i] = str_ptr -> elt + array2[j];
This latter involves three memory operations, so there are at least three opportunities for a page-fault to occur. For each of these, the processor must save enough state information to allow the OS to figure out what happened, fix things, and restart or continue the instruction.

In contrast, in a load/store architecture, only the lw and sw instructions could cause a memory fault. The complexity of interrupt and fault handling is greatly simplified, so the chip design itself is simpler. This leads to a more efficient use of chip real-estate, smaller die sizes / shorter signal paths, and faster processors.

There are some specialized registers. at is reserved for the assembler. $zero is always zero. The k registers are reserved for use by the kernel (during interrupts / faults). See the SPIM handout, table 2 on page 10.

You received a copy of SPIM S20 documentation -- includes a MIPS instruction set summary and a description of how to use the SPIM program.

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