CSE 30 -- Lecture 5 -- Oct 13

Our one-instruction computers makes explicit some computer architectural issues. To do anything interesting like ``efficient'' array indexing or subroutines, self-modifying code is needed. Almost all operating systems today forbid self-modifying code. Why is this? There are programming issues, OS efficiency issues, as well as hardware architectural reasons for this. Separate instruction and data caches (``Harvard architecture'' -- this used to mean separate memories all together) uses chip space much more efficiently.

There are (at least) two design choices when implementing data caches: the D cache can be either a write-through cache or a write-back cache. What is the difference? Is one more efficient than the other?

Another point to note about the OIC is that it takes a lot of instructions to get anything done -- not just number of instructions to write, but dynamically, number of instructions executed. Can you imagine how to compare two unsigned numbers? The only comparison operation is equality to zero, so how do we decide if one memory location contains a number that is larger or smaller than the number in another memory location?

Even though the OIC is ``simple'' and has a very much reduced (to a singleton) instruction set, it is not really a RISC architecture. Why is this? RISC is more a set of engineering principles than a blind set of rules -- the goal of the simplicity is increased performance or increased cost effectiveness (performance per dollar spent in the design and the implementation -- the unit cost). OIC programs have very poor instruction density, and are overly simple: the number of subz instructions executed to do anything meaningful is huge.

In the MIPS instruction set architecture, we have many more instructions. This architecture is much more complex than that of the OIC, but is still much simpler than an architecture such as the Intel x86 architecture. Important features to note are instruction regularity -- three operands, load/store,

Reading assignment: Chapter 3.

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