# CSE 30 -- Lecture 2 -- Oct 1

This lecture covered number representations, the related-base-change algorithm, and touched on RISC and CISC instruction designs.

Polynomial representation of a number: in base 10, the number n = 524398, denoted 524398(10) equals 5 * 105 + 2 * 104 + 4 * 103 + 3 * 102 + 9 * 101 + 8 * 100. Suppose I want to express this same number in base 2. The ``ones'' binary digit (or bit) can be determined as follows: we write n = m1 * 2 + n0. We get n0 = 0, and m1 = 262199. We write m1 = m2 * 2 + n1, and get n1 = 1 and m2 = 131099. Repeated division by the base and writing the remainder down (in reverse order) gives 1000 0000 0000 0110 1110 (2).

That was the general algorithm for getting the representation of a number in a different base. If the original and destination bases are related, however, we can do better. Suppose we have
n = d2 * B2 + d1 * B1 + d0 * B0
where di are the digits of the number n in base B. Suppose we have (lowercase) b where B = b2, and we wish to write down n in base b. Well, each digit di is in the range 0, ..., B-1, and can be written as a two base-b digit number c2i+1 * b + c2i. Thus,
n = d2 * B2 + d1 * B1 + d0 * B0
= (c5 * b + c4) * B2 + (c3 * b + c2) * B1 + (c1 * b + c0) * B0
= (c5 * b + c4) * b4 + (c3 * b + c2) * b2 + (c1 * b + c0) * b0
= c5 * b5 + c4 * b4 + c3 * b3 + c2 * b2 + c1 * b1 + c0 * b0

Thus, each base B digit turned into two base b digits. Doing the reverse conversion, of course, would involve grouping two base b digits together to form a base B digit.

Assignment: perform the following base conversions.

1. 387(10) = ?(3)
2. 78354(9) = ?(3)
3. F786(16) = ?(8)
4. 12112(3) = ?(9) There was a typo here.

Due before class next Wednesday. Expect to see a question on this on the midterm.

Missing from this web page: design philosophy behind RISC. Time to complete instructions. Clock cycle times. Simple instructions finish fast, complex ones take longer. Some CISCy computers (e.g. VAX) had instructions that no compiler knew how to generate. Profiling programs to get dynamic execution traces. Optimal use of chip real estate. More registers in RISCs. Instruction density and memory bandwidth.

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