CSE 120: Homework #3
Out: Thursday October 31
Due: Monday November 18 at 11:59pm
- Nachos VM Worksheet (We strongly recommend doing this worksheet early as you start to work on project #2)
When using physical addresses directly, there is no virtual to
physical translation overhead. Assume it takes 100 nanoseconds to
make a memory reference. If we used physical addresses directly, then
all memory references will take 100 nanoseconds each.
- If we use virtual addresses with page tables to do the translation,
then without a TLB we must first access the page table to get the
approprate page table entry (PTE) for translating an address, do the
translation, and then make a memory reference. Assume it also takes
100 nanoseconds to access the page table and do the translation. In
this scheme, what is the effective memory reference time (time to
access the page table + time to make the memory reference)?
- If we use a TLB, PTEs will be cached so that translation can
happen as part of referencing memory. But, TLBs are very limited in
size and cannot hold all PTEs, so not all memory references will hit
in the TLB. Assume translation using the TLB adds no extra time and
the TLB hit rate is 75%. What is the effective average memory
reference time with this TLB?
- If we use a TLB that has a 99.5% hit rate, what is the effective
average memory reference time now? (This hit rate is close to what
TLBs typically achieve in practice.)
- Consider a 32-bit system with 1K pages and simple single-level paging.
- With 1K pages, the offset is 10 bits. How many bits are in the
virtual page number (VPN)?
- For a virtual address of 0xFFFF, what is the virtual page number?
- For a virtual address of 0xFFFF, what is the value of the offset?
- What is the physical address of the base of physical page number 0x4?
- If the virtual page for 0xFFFF is mapped to physical page number 0x4,
what is the physical address corresponding to the virtual address 0xFFFF?
- [Crowley] Suppose we have a computer system with a 44-bit
virtual address, page size of 64K, and 4 bytes per page table
- How many pages are in a virtual address space?
(Express using exponentiation.)
- Every process has its own page table, and every page table has a
master page and many secondary pages. Suppose we arrange for each
kind of page table page (master and secondary) to have the size of a
single page frame.
How will the bits of the address be divided up among the offset, index
into a secondary page, and index into the master page?
- Suppose we have a 4 GB program such that the entire program
and all necessary page tables (using two-level pages from above)
are in memory. (Note: It will be a lot of memory.)
How much memory, in page frames, is used by the program,
including its page tables?
- [Crowley] Suppose we have an average of one page fault every
20,000,000 instructions, a normal instruction takes 2 nanoseconds, and
a page fault causes the instruction to take an additional 10
milliseconds. What is the average instruction time, taking page
faults into account? Redo the calculation assuming that a normal
instruction takes 1 nanosecond instead of 2 nanoseconds.
- [Tanenbaum] If FIFO page replacement is used with four page
frames and eight pages (numbered 0–7), how many page faults will
occur with the reference pattern 427253323126 if the four frames are
initially empty? Which pages are in memory at the end of the
references? Repeat this problem for LRU.
- If many programs are kept in main memory, then there is almost
always another program ready to run on the CPU when a page fault
occurs. Thus, CPU utilization is kept high. If, however, we allocate a
large amount of physical memory to just a few of the programs, then
each program produces a smaller number of page faults. Thus, CPU
utilization is kept high among the programs in memory.
What would the working set algorithm try to accomplish, and why?
(Hint: These two cases represent extremes that could lead to
- [Silberschatz] Consider a demand-paging system with the following
CPU utilization: 20%
Paging disk: 97.7% (demand, not storage)
Other I/O devices: 5%
For each of the following, say whether it will (or is likely to)
improve CPU utilization. Briefly explain your answers.
a. Install a faster CPU
b. Install a bigger paging disk
c. Increase the degree of multiprogramming
d. Decrease the degree of multiprogramming
e. Install more main memory
f. Install a faster hard disk, or multiple controllers with multiple hard disks
g. Add prepaging to the page-fetch algorithms
h. Increase the page size