Fall 2014 CSE 140L
Digital Systems Laboratory(Sec-B)
by
Dr. Choon Kim
CSE Dept., UCSD
News & Updates
21. 12/10/14: [Dr. Kim] Reminder:
CAPE Survey: All students are
reminded to participate in
CAPE Survey.
20. 12/04/14: [Dr. Kim] About LAB4 Part4(clock stopping
switch): A switch based on the base design code
and a switch based on the golden solution may be
different. Either one is accepted as a valid solution for Part4.
19. 11/20/14: [tutor Priyanka] my Office hour
change:
THIS WEEK ONLY(11/17-21): Thu(9:30-1pm)
hours cancelled.
18. 11/19/14: [Dr. Kim] LAB#4 assigned(Due: Wed. 6pm 12/10/14)
17. 11/18/14: [tutor Harry] my Office hour
change:
THIS WEEK ONLY(11/17-21):
Fri.(1-6pm)
hours cancelled.
16. 11/17/14: [tutor Vera] my Office hour
change:
THIS WEEK ONLY(11/17-21):
Thu. hours moved
to
Fri(1-5pm)
NEXT WEEK ONLY(11/24-28):
Wed. hours moved
to
Tue(1-5pm)
[tutor Tim] my Office hour change:
THIS WEEK ONLY(11/17-21):
Tue. hours moved
to Thu(9-11am)
15. 11/12/14: [tutor Angie] my Office hour
change
THIS WEEK ONLY(11/10-14): Wed. hours moved to Thu(1-2pm, 4-6pm).
14. 11/10/14: [Dr. Kim] Triple-grading process of
midterm has
been completed and the score is available on Ted. The
graded midterm paper is kept at Dr. Kim's office and will not be returned to
student. If desired, student can review his/her midterm grading with Dr. Kim
during Dr. Kim's office hour until the end of November(11/30/14). Email Dr.
Kim your CID & Date of your coming first before coming to your reviewing
meeting.
[tutor
Jack] my Office hour
changed
PERMANENTLY from today(11/10/14):
See Tutor Office Hours section for my new office hours.
13. 11/03/14: [Dr. Kim] LAB#3 assigned(Due: Wed. 6pm 11/19/14)
12. 11/03/14: [tutor Wendy] my Office hour
change
THIS WEEK ONLY(11/03-07):
Mon. hours moved
to
Fri(9-11am, 1-2pm).
11. 10/28/14: [Dr. Kim] Info:
midterm is
a closed-book exam. Nothing other than pen/pencil and
eraser are allowed to use.
10. 10/23/14: [tutor Vera] my Office hour
change
THIS WEEK ONLY(10/20-24):
Thu. hours moved
to
Fri(1-5pm).
09. 10/22/14: [Dr. Kim] Following is a rule
about exam(see "Exams" section).
"Please take note of the following addition to the Academic Integrity Agreement:
All midterm and final exam information is confidential and MUST NOT be shared
with other students. Your cooperation is required. Any non-compliance may be
considered a breach of academic integrity and will be reported."
08. 10/22/14: [tutor Angie] my Office hour
change
TODAY ONLY(10/22): Wed. 2-3pm.
[tutor Angie] my Office hour change
NEXT WEEK ONLY(10/27-31):
Mon. hours moved
to
Fri(1-4pm
-> 12-3pm).
07. 10/21/14: [tutor Brian] my Office hour
change
THIS WEEK ONLY(10/20-24):
Wed. hours moved
to
Fri(10-12pm).
[tutor Wendy] my Office hour change
THIS WEEK ONLY(10/20-24):
Wed. hours moved
to
Fri(9-11
& 1-2pm).
[tutor Priyanka] my Office hour cancelled
TODAY ONLY(10/21).
06. 10/20/14: [Dr. Kim] A typo has been corrected on the
Section PART4 of LAB2 document.
"....since the moment when SW[6]
goes up(i.e., when Part4 selected)" was corrected to
"....since the moment when SW[8] goes up(i.e.,
when Part4 selected)"
05. 10/17/14: [tutor Tim] my Office hour change
NEXT WEEK ONLY(10/20-24):
Tue
&
Wed. hours moved
to
Thu(9-11am) and Fri(10-1pm).
04. 10/16/14: [Dr. Kim] Reminder:
midterm (Thu. 10/30/14 during
Lecture class, 5-6pm)
03. 10/15/14: [Dr. Kim] LAB#2 assigned(Due: Wed. 6pm 10/29/14)
02. 10/03/14: [Dr. Kim] NEW Exam schedule:
one midterm and
Final exam(see "Exams" section
for details). In other words, the initial plan(two midterms) has been
changed to this new plan.
01. 10/02/14: [Dr. Kim] 1) First day of FA14 CSE140L (Sec-B).
2) LAB#1 assigned(Due: Wed. 6pm 10/15/14)
3) CSE3219LAB access code is available on TED(see My Announcements).
Course Description
Implementation with computer-aided design(CAD) tools for combinational logic
minimization and state machine synthesis. Hardware construction of a small
digital system. See http://www.cs.ucsd.edu/cse140L.
Instructor
Dr. Choon Kim, office: CSE3218, office phone: 858-246-0320, email:
chk034@eng.ucsd.edu
Office Hours(see tutor office hour section below).
About Choon Kim
Message from Instructor
Welcome to CSE140L class! The knowledge & skills that you will learn from
this class can be very useful in your engineering career in the future. Also the
LAB projects can be fun to do. However this class demands your
significant amount of effort and
real hard work. I wish all of you a good luck in my
class.
Websites
http://cseweb.ucsd.edu/classes/fa14/cse140L-b/ For Syllabus,
News & Updates, Lecture notes, LAB
assignments, etc.
https://ted.ucsd.edu/webapps/login/ For Submitting LABReport, Checking grade,
Discussions among students , etc.
Course Information Sources
1. This course webpage and
instructor are
ONLY valid information sources for any
course-related issues(e.g., LAB Projects, Reports, Grading, Exam or any other
issues.)
2. If student has a question
about any issue which is not answered
on this course webpage,
student should ask instructor to get a clear answer. Also, just in case an
information from instructor is inconsistent
with the information on this course web page, discuss with instructor
immediately to get a correct answer.
3. Therefore any excuse based on source other than above two(course webpage and
instructor) is NOT accepted by instructor.
For example, an excuse like "A tutor said this...", "A friend
of mine said that...", "I heard it from somebody who took this class
before...", etc. is not acceptable.
4. Student is required to check this webpage
frequently, at least twice a day, to avoid missing
a time-critical information.
Missing class(Lecture and Discussion)
- Both Lecture and
Discussion are official part of this course. Student is required to attend
both.
- When student misses any of Lecture or
Discussion, he/she is solely responsible to recover all the missing information as soon
as possible. Instructor will not repeat his teaching for the student missing
class.
- If student is not able to attend
regularly both for any reason(e.g., time conflict with other class enrolled), he/she
misses 50% of class meetings and, therefore, he/she should NOT take this course.
- It has been observed in the past that missing
class was one of common reasons of failure or
low grade in this course.
Tutors
Rules about tutors:
- Tutors are available for student. Student
may get help from them. However following rules are applied.
- Any
information from tutor must be treated by student as
an unconfirmed
or unverified
reference. Student is responsible to check and confirm the correctness
and the validity of information obtained from tutor.
- Therefore any excuse by
student blaming tutor for his/her own fault is NOT
accepted by instructor(e.g., "Tutor said this..." or "Tutor said
that....", etc.).
-
Student, not tutor, is responsible for any work in this course.
Tutor location:
CSE3219LAB(If the 3219LAB room is
reserved or occupied by other event which may occur from time to time, tutor may meet student at the lobby area in
the front of the CSE3226)
Tutor Office Hours:
Tutor and Instructor office hours can be changed whenever necessary.
Student should always check the latest office hour information first on this
webpage. All tutor office hours are during daytime only, 9am - 6pm.
Tutor:
Mon Tue Wed Thu Fri
Angie Nguyen 3-6 4-6 12-3
(ann045@ucsd.edu)
Brian T Ly
10-12 10-12
10-12 10-12
(btly@ucsd.edu)
Jack(Chao) Li
9-12
9-11 9-12
(chl218@ucsd.edu)
Harry(Hyunwoo) Cho 1-2:30
4:30-6
1-6
(hyc046@ucsd.edu)
Priyanka Gupta
12-1
9:30-1
9:30-1
(p8gupta@ucsd.edu)
Timothy J Kua 10-1
9-11
10-1
(tkua@ucsd.edu)
Tony Lu
9-12 9-12
9-11
(tzlu@ucsd.edu)
Wendy Kwan
10-1 10-1
11-1
(w1kwan@ucsd.edu)
Yingbai He
11:30-2:30 11:30-1,
2-3:30
11:30-1:30
(y7he@ucsd.edu)
Vera(Zhihui) Xia 1-5 1-5
(zhxia@ucsd.edu)
Dr. Choon Kim 2-4 2-4
(chk034@eng.ucsd.edu)
Exams: (closed-book
exam. Nothing other than pen/pencil and eraser are allowed to use.).
- There is
one midterm during class hour(see Class
Schedule section below for midterm schedule).
- There is a final exam
during final exam week(see UCSD Class Schedule web
page for final exam schedule).
- There is NO makeup
exam if student misses exam.
- If student has a valid
and acceptable reason for missing exam due to
uncontrollable circumstances(e.g., medical emergency verified by doctor's letter &
document), he/she must discuss with Dr. Kim as soon as possible showing proper
documents.
-
Rule about exam.
"Please take note of the following addition to the Academic Integrity Agreement:
All midterm and final exam information is confidential and MUST NOT be shared
with other students. Your cooperation is required. Any non-compliance may be
considered a breach of academic integrity and will be reported."
Class Schedule(The
schedule can be changed if necessary)
------------------------------------------------------------------------------------------
Week #1 (10/02) Introduction to course overall, LAB HW, SW, doc information, CAD Process, LAB#1
assignment
Week #2 (10/09) Intro. to CMOS, Gates, Logic Design(Comb.
Logic), FPGA, Introduction to Verilog HDL
Week #3 (10/16) Comb. Ckt(cont'd), Sequential Ckt
Concept, Verilog HDL(cont'd), LAB#2
assignment
Week #4 (10/23) Sequential Circuit Design, Verilog HDL(cont'd),
Week #5 (10/30) *** Midterm during class ***,
LAB#3 assignment
------------------------------------------------------------------------------------------
Week #6 (11/06) FSM,
Week #7 (11/13) FSM(cont'd),
Week #8 (11/20) Practical Sequential Logic Design,
LAB#4 assignment
Week #9 (11/27) UCSD Thanksgiving Holiday - no class
------------------------------------------------------------------------------------------
Week #10 (12/04) Practical Sequential Logic Design(cont'd),
Week #11 (12/11) Practical Sequential Logic Design(cont'd), ,
***** Final Exam Week(see
UCSD Class Schedule web page for time schedule)
***********
Recording or Taking picture during class:
No recording or taking picture is allowed during class
without written consent from instructor.
Textbook :
No textbook is required. The textbook of CSE140 class is a good reference for this class.
Computer & OS needed for class(Window PC)
- Our CAD SW("Quartus") runs on Window.
- Student can use student's own PC or LAB PC
which is available at CSE3219LAB room.
CSE3219 LAB Room
1. The CSE3219 LAB is
open 24 hours, 7 days a week. In other words, student can access LAB anytime. Access passcode to the LAB will be announced for
students on TED. The 3219LAB has Window PCs to be used by student. First read
CSE3219Lab General Policies
before using LAB.
2. CSE3219 LAB is a ***shared***LAB with other classes and events.
Various hours/time slots are reserved for others frequently. Student
cannot use 3219 LAB room or LAB PCs when they are reserved for other
class or events. If the 3219LAB room is reserved or
occupied by other event, tutor may meet student at the lobby area in front of the CSE3226. Student needs to check the LAB Schedule
sheet posted on the LAB door or the event "CSE 3219" on Google Calendar
if available.
3. While LAB is available to student anytime, I have reserved CSE3219LAB room 5-7pm M-Th for our
CSE140L(Sec-B) class students(However, please remember a fact that the LAB is a ***shared*** facility and our reserved time can be overridden
by more important or urgent event of department)
Class ID(CID)
- An unique 3-digit number called Class ID(CID) will be assigned to each student.
- Check
your TED account "My Grade" window to find your CID.
- The CID will be used throughout the course to
identify a student. The CID starts from 001 up to 300.
HW FPGA Board & CAD SW tools required for this class
1. HW FPGA Board
Altera Cyclone II FPGA Starter Development
Board(a.k.a DE1
Board).
A student is responsible to prepare one
working board for the class. Student can
purchase the board any way he/she wants. (Advise: The bookstore normally
has some boards in stock, so it
may be a good idea to check with bookstore before their stocks are all sold out.)
2. CAD SW(free download from Altera site --
see the link below)
Altera Quartus II Web Edition Software
v9.0 Service Pack 2 -- DO NOT use
different version
- If student uses CSE3219 LAB PC, it has a CAD SW installed already.
- If student uses his/her
own PC, download SW from the following Altera website, and
install it on your computer.
https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v90.jsp
The executable file name is "90sp2_quartus_free.exe" and the file size is about
1.31GB.
LAB Project(Working,
Submission and Demonstration)
Step 1. Working on LAB
project
- All LAB projects must be done by student
individually.
No group work is allowed(i.e., students are NOT allowed to pair up).
- Discussion of information
not directly related to the solution is
allowed between students(e.g., general discussion of Verilog, CAD SW, HW Kit, etc.).
However, sharing of
solution
or information directly related to the solution between
students is strictly prohibited.
- Advice: It is highly
recommended to start the
project as early as possible for better chance of successful completion.
It is not a good idea to delay
project until the LAST DAY of the project period.
You
may have a pretty good
chance of missing due time.
Step 2. Submission
of Report & Design files to TED system
2.1 Student must submit a file to Ted system first before making a
demonstration.
Each student should put following two files into a single ZIP file(ZIP file
name is "LxCyyy.zip"), and
submit it to TED system by
due date & time.
file#1) a PDF file of your LAB Report(file name is "ReportLxCyyy.pdf")
file#2) a ZIP file of your LAB Project design directory(file name is "ProjectLxCyyy.zip")
where, x=LAB
Number, yyy=your CID.
For example,
For LAB1, student with CID#009
should submit L1C009.zip which contains
ReportL1C009.pdf and ProjectL1C009.zip.
Another Example:
For LAB3, student with CID#196
should submit L3C196.zip which contains
ReportL3C196.pdf and ProjectL3C196.zip.
Notes: ---------
- TED accepts your submission
up to 3 times before
due for each LAB. NO more than 3 times resubmission is allowed by TED.
-
No late submission
is accepted by TED.
- If student
a)
misses submission
or b) submits invalid file(s),
he/she will
receive zero(0)
point for the LAB regardless of Demonstration.
2.2
Contents of LAB#4
Report------------------------------------------------------------
1) Use this
LAB4_Report_cover_page.docx The report has no more than 10 pages excluding
cover page.
2) Procedural description of work done to complete the project
3) ***ONLY UPDATED PART*** of Verilog HDL codes
4) ***ONLY UPDATED PART*** of State Diagram of your design
5) A screen copy of Compilation Report - Flow Summary(Clearly mark the
Percentage(%) value of "Total logic elements")
Contents of LAB#3 Report------------------------------------------------------------
Use this
LAB3_Report_cover_page.docx The report has no more than 10 pages
excluding cover page.
a) Procedural description of work done to complete the project
b) Complete Verilog HDL codes of your design(use
small fonts, multiple columns, multiple sides, etc. to save pages)
c) State Diagram of your design
d) A screen copy of Compilation Report - Flow Summary(Clearly mark the
Percentage(%) value of "Total logic elements")
Contents of LAB#2
Report------------------------------------------------------------
1) Use this
LAB2_Report_cover_page.docx
2) Provide the followings in your report.
a) Your work description(i.e.,
Describe what & how you did in detail to complete the Parts in LAB#2)
b) A Flowchart drawing of your design(similar to a
Flowchart when you write a SW programming codes)
This is a graphical presentation of your LAB#2
work using the flowchart format. Each student's presentation would be
different depending his/her work flow. There is, therefore, no standard solution
or example. If you are not familiar with the concept of flowchart, see
http://en.wikipedia.org/wiki/Flowchart
c) Complete Verilog Codes
d) Flow Summary in Compilation Report. Clearly mark the
Percentage(%) value of "Total logic elements"
e) Timing Analyzer Summary in Compilation Report. Clearly
mark the "Worst-case tco" row
Contents of LAB#1 Report------------------------------------------------------------
1) Use this LAB1_Report_cover_page.docx
2) The Report must be written well and clean enough for grader to understand it
easily in order to receive any credit. It has no more than 10 pages
excluding cover page
3) You should provide the followings
in the report for LAB#1.
a) Your work description(i.e., Describe what &
how you did in detail to complete the Parts in LAB#1)
b) Schematic diagram(hint: There are many different ways to capture the
diagram and paste it on your report. You can do any of them. )
c) Functional simulation diagram (hint: similar to the one shown in the example diagram in
the LAB#1 Document)
d) Timing simulation
diagrams. You must show at least one timing delay value on your waveform, like
the one shown in the example diagram in the LAB#1 Document
e) Timing Analyzer Summary(hint: it is available after you compile
your design successfully)
Step 3. Demonstration
of your project to Demo Reviewer(instructor or tutor)
3.1. A student who
made a submission to TED is allowed to demonstrate
his/her design to Demo Reviewer(instructor or tutor) by due
date &
time.
Notes: ---------
-
The LAB
Project design on demonstration
must be the same one
which was submitted to
TED. Otherwise it is regarded as
cheating and
zero(0) point
will be assigned to student.
- Demonstration is performed
during office
hours with first-come, first-served basis. No appointment
will be made.
- No late Demo is allowed.
No
defective malfunctioning DE1 board is allowed for Demo.
- ONLY one
Demo is allowed per LAB. Another Demo
after fixing error discovered during Demo is NOT allowed.
- If a student
misses Demonstration,
he/she will
get zero(0) point
for the LAB regardless of the submission to TED.
3.2 Student must bring a
hardcopy of LAB Report to
demo reviewer(instructor or
tutor) to start demonstration.
3.3 For demonstration, DE1 board should have been programmed with
your design using AS(Active Serial)
method, not JTAG method.
3.4 During LAB Project Demonstration,
-
NO reprogramming of DE1
board is allowed during demonstration.
-
All the Parts of a LAB
project should be tested continuously without any interruption of reprogramming.
-
Only exception of this rule is LAB4(which may require reprogramming during demo.).
Grading
1. 100 points total:
All LABs = 70 points(10 points for LAB#1, 20
points for each of remaining three, LAB#2-4)
All exams
= 30 points(15 points for midterm, and 15 points for final exam)
2. LAB#1:
a) 5 points for Demonstration. The student score is determined by
tutor/instructor based on the quality of LAB Demo output result.
b) 5 points for a Report. The student score is determined by
tutor/instructor based on the quality of LAB Report.
LAB#2-4:
a) 15 points for Demonstration. The student score is determined by
tutor/instructor based on the quality of LAB Demo output result.
b) 5 points for a Report. The student score is determined by
tutor/instructor based on the quality of LAB Report.
3. NO Partial Credit Grading Policy
- Each LAB project
consists of
several Parts(for example, LAB#1 may have five Parts).
- You will get either
full score or
zero(0) on
each Part of the LAB.
In other words,
NO partial score is
assigned to each Part.
- A full core is given
if and only if
ALL required features of the Part are implemented and
demonstrated correctly. Otherwise, zero(0) will be assigned.
- A partial score, if
given, is a clerical error and will be converted to zero(0) point.
- An
exception, if any, can be made
ONLY by instructor in a truly deserving case in special circumstance.
Notes:
In digital system design engineering, much of the learning & effort takes place
in debugging the last small part(let's say, last 1%, for example) and making the
design working perfectly. There is a **huge** difference in quality of work
between "working perfectly" and "almost working but not perfectly(a.k.a.
inferior quality engineering)". My 140L class aims at high quality engineering
education. Each part of our LAB is the smallest independent function which has
small scale with minimum complexity. It does not deserve a partial credit for
inferior quality engineering design.
4. A plus(+) and minus(-) grading scheme will be used in the
final letter grade assignment(e.g., A+ A A-, B+ B B-, C+ C C-, etc.).
Academic Dishonesty & Student Conduct Policy
As student in this offering of CSE 140L, you are expected to know and abide by
the UCSD Policy on Integrity of Scholarship (as described in the
Student Conduct
Code in the UCSD General Catalog), the Jacobs School of Engineering
Student
Honor Code, and the course policy described here.
Any student violating UCSD's Academic Dishonesty or UCSD's Student Conduct
policies will earn an 'F' in the course and will be reported to their college
Dean for administrative processing. Committing acts that violate Student Conduct
policies that result in course disruption are cause for suspension or dismissal
from UCSD.
--------------------- The End ------------------