Fall 2013 CSE 140L
Digital Systems Laboratory
by
Dr. Choon Kim
CSE Dept., UCSD
News & Updates
24. 12/17/13: [Dr. Kim] Final Exam & Letter
Grade information is available on Ted Announcement and MyGrade.
23. 11/25/13: [Eddie] On my Wed. Nov. 27th office
hours(10am-2pm), Angie will replace my hours from 10am to 12pm and Jason
will replace my hours from 12pm to 2pm.
22. 11/24/13: [Larry] My regular office hours have been
permanently changed to Tue. 9am - 5pm effective today.
[Zack] My office hours on this Thanksgiving week only has
been changed to Monday(11/25/13) 9am - 5pm.
21. 11/22/13: [Dr. Kim] You have to put the
submission time stamp on LAB#4 hard-copy cover page to demonstrate. You
can copy & paste your submission time stamp from [Review Submission History]
window on Ted, e.g., Submission ( November 22, 2013 2:47:41
PM PST ). You don't put this submission time stamp on zip
file when submitting.
20. 11/20/13: [Dr. Kim] LAB#4 assigned. Submission Due = Demo Due =
Thu. 6pm
12/05/13.
19. 11/13/13: [Dr. Kim] One more "Err
" display condition has been added on LAB#4 assignment document,. See the
Section 4.3).
The condition is: ****Credit Card input when hex[3:0]=3500(i.e., when
Deposit=35 and Change=00) ****. Play with the golden solution first if you
have a question.
18. 11/12/13: [Dr. Kim]
LAB#3
Sub&Demo Due date&time has been changed to
Thu. 6pm 11/21/13 (from original
Wed. 1pm 11/20/13).
17. 11/09/13: [Dr. Kim] Midterm score is available on
Ted. The solution has been announced and reviewed during class. Student can
review his/her exam paper with me in my office during my office hours until
12/06/13.
16. 11/07/13: [Dr. Kim]
LAB#3 assigned. Submission Due = Demo Due =
Thu. 6pm 11/21/13(new
due date&time)
15. 11/05/13: [Dr. Kim] My regular office hours have
been changed permanently to W Th. 11am -1pm. My "Open-door office hour" is
still valid.
14. 10/24/13: [Dr. Kim] Reminder: Midterm
on Fri. 1-1:50pm, 11/1. It's a closed-book
exam. Nothing other than pen/pencil with eraser is allowed.
13. 10/23/13: [Dr. Kim] A hint for Verilog coding for
our LAB: The initial construct
and the delay specification(#<n>, e.g.,
#4 ....) in Verilog are
not needed for our LAB projects. See lecture notes for more.
12. 10/22/13: [Dr. Kim] Job info.:
job_tivo_letter
job_tivo_Information
Session - UCSD
11. 10/18/13: [Dr. Kim] LAB#2
Sub&Demo Due date&time has been changed to Mon.
3pm 11/04/13 (from original
Thu.
6pm 10/31/13).
10. 10/18/13: [Eddie] My regular office hours on T,Th
12:30-1:30pm have been permanently moved to M,W 1-2pm. So, my new regular
office hours are M 10-2pm, W 10-2pm. Please see updated Tutor Office
Hours.
09. 10/16/13: [Eddie] My today's office hour 10-1pm has been
cancelled due to medical emergency. Instead I will have Oct.
18(Fri.) 10-1pm to replace today's missing office hours.
08. 10/15/13: [Dr. Kim] About LAB#2 Report section b)
--- The section b) is a graphical presentation of your LAB#2 work
using the flowchart format. Each student's presentation would be different
depending his/her work flow. There is, therefore, no standard solution or
example. If you are not familiar with the concept of flowchart, see
http://en.wikipedia.org/wiki/Flowchart
[Wai Ho] My Oct. 16(Wed.) office hour 10-12pm has been moved to Oct.
18(Fri.) 4-6pm.
07. 10/12/13: [Dr. Kim] Recommended Verilog books. Note
that numerous good Verilog books are available in the world and each book is
different in various ways. In the end you yourself should find a
book best suitable for your own unique situation.
a) Verilog HDL (2nd Edition) -- 2003 by Samir Palnitkar
b) A Verilog HDL Primer (Third Edition) -- 2005 by J.
Bhasker
06. 10/10/13: [Dr. Kim] LAB#2 assigned. Submission Due = Demo Due =
Mon. 3pm 11/04/13(new
due date&time)
05. 10/06/13: [Dr. Kim] The LAB score is available on
Ted within a week(7 days) after Demo. Student is responsible for checking
his/her LAB score on Ted quickly to make sure it is correct. If student has a
question regarding a LAB score on Ted, he/she should first contact & discuss
with the tutor who had reviewed his/her Demo. If not resolved, then contact Dr.
Kim. Always provide CID number when communicating with tutor/Dr. Kim.
04. 10/05/13: [Dr. Kim] Extra chance to see me("Open-door
office hour") --- Student may
ask me a question in my office when he/she sees my office door is open. If I am
not busy, I will be happy to help student. However if I am busy, I cannot help
and will ask student to come back later.
03. 10/03/13: [Dr. Kim] Reminder ---
Tutor(& Dr. Kim) office hours can be changed when an unexpected time conflict
happens. Student should check the latest office hour list first if he/she wants
to meet a specific person.
[Justin] My office hour on Oct. 7 will be 11:30-1pm and 2:30-6pm
(instead of 1-6pm).
02. 09/29/13: [Dr. Kim] My Oct. 2
office hour has been moved to Oct. 8 at the same time.
01. 09/27/13: [Dr. Kim] 1) Class starts
at 12pm(Discussion) Fri. 09/27/13.
2)
LAB#1 assigned. Submission Due = Demo Due = Thu.
6pm 10/10/13
3) CID and 3219LAB access code are available on Ted( <your CID>/999 ).
Course Description
Implementation with computer-aided design(CAD) tools for combinational logic
minimization and state machine synthesis. Hardware construction of a small
digital system. See http://www.cs.ucsd.edu/cse140L.
Instructor
Dr. Choon Kim, office: CSE3218, office phone: 858-246-0320, email:
chk034@eng.ucsd.edu
Office hours(see tutor section below)
Message from Instructor
Welcome to CSE140L class! The knowledge & skills that you will learn from
this class can be very useful in your engineering career in the future. Also the
LAB projects can be fun to do. However this class demands your
significant amount of effort and
real hard work. I wish all of you a good luck in my
class.
Websites
http://cseweb.ucsd.edu/classes/fa13/cse140L-a/ For Syllabus,
News & Updates, Lecture notes, LAB
assignments, etc.
https://ted.ucsd.edu/webapps/login/ For Submitting LABReport, Checking grade,
Discussions among students , etc.
Course Information Sources
1. This course webpage and
instructor are
only valid information sources for any
course-related issues such as LAB Projects, Reports, Grading, Exam or other
issues. If student has a question which is not answered on this course webpage(or
if an information from instructor is inconsistent
with the information on this course web page),
student should ask instructor to get a clear answer.
2. Therefore any excuse based on source other than above two
is not accepted by
instructor. For example, an excuse like "A tutor said this...", "A friend of
mine said that...", "I heard it from somebody who took this class before...",
etc. is not accepted.
3. Student is required to check this webpage
frequently, at least twice a day, to avoid missing
time-critical information.
Tutors
Rules about tutors:
- Tutors are available for student. Student
may be able to get help from them.
- Remember a fact that student, not tutor, is responsible for completing project successfully.
- Any
information from tutor must be treated by student as
an unconfirmed
or unverified
reference only. Student is responsible to check and confirm the correctness
& the validity of information obtained from tutor.
- Therefore any excuse by
student based on tutor's help(e.g., "Tutor said this..." or "Tutor said that....", etc.) is
not
accepted by instructor.
Tutor location: CSE3219LAB (If the 3219LAB room is
reserved or occupied by other event, tutor will meet student at the lobby area in front of the CSE3226)
Note: Tutor(& Dr. Kim) office
hours can be changed when an unexpected time conflict happens. Student should
check the latest office hour list first if he/she wants to meet a specific person.
Tutor List and Office hours:
Mon
Tue Wed
Thu
Angie Nguyen <ann045@ucsd.edu>:
12-5pm 12-3pm
Eddie An <hman@ucsd.edu>:
10-2pm
10-2pm
Zach(Jae-hyun) Lee <jal198@ucsd.edu>: 9-1pm 3:30-7:30pm
Jason K Yohena <jyohena@ucsd.edu>:
9-12pm
3-5pm
2-5pm
Jonathan J Shamblen <jshamble@ucsd.edu>:
4-8pm
4-8pm
Justin Kang <jsk071@ucsd.edu>:
1-6pm
Larry Huynh <lahuynh@ucsd.edu>:
9am - 5pm
Wai Ho Leung <whleung@ucsd.edu>: 10-12pm, 2-4pm 10-12pm 5-7pm
Dr. Kim(instructor) <chk034@eng.ucsd.edu>:
11am-1pm
11am-1pm
(In addition, Dr. Kim has "Open-door office hour". Student may ask Dr. Kim a
question in his office when student sees his office door is open. If he is not
busy, he will be happy to help student. However if he is busy, he cannot help
and will ask student to come back later.)
Class Schedule(Time, Place):
Check
Tritonlink(Schedule
of Classes)
About missing or skipping class
- Student is required to attend
all the lectures and the discussions.
- If a student misses a class, he/she is responsible
to recover all the missing information as soon as possible.
- Missing or skipping a
class is one of common reasons of failure or
low grade.
Weekly Class Schedule(note:
It can be changed if necessary)
------------------------------------------------------------------------------------------
Week #1 (9/27) Introduction to course, LAB HW, SW, doc information, CAD Process, LAB#1
assignment
Week #2 (10/4) Intro. to CMOS, Gates, Logic Design(Comb.
Logic), FPGA, Introduction to Verilog HDL
Week #3 (10/11) Comb. Ckt(cont'd), Sequential Ckt
Concept, Verilog HDL(cont'd),
LAB#2
assignment
Week #4 (10/18) Sequential Circuit Design, Verilog HDL(cont'd),
Week #5 (10/25) Sequential Circuit Design(cont'd), FSM
------------------------------------------------------------------------------------------
Week #6 (11/01) ***Midterm exam(closed-book) on Fri. 1-1:50pm
11/01/13 & LAB#3 assignment
------------------------------------------------------------------------------------------
Week #7 (11/8) FSM(cont'd),
Week #8 (11/15) Practical Sequential Logic Design,
Week #9 (11/22) Practical Sequential Logic Design(cont'd),
LAB#4 assignment
Week #10 (11/29) NO class -- UCSD Thanksgiving
Holiday
Week #11 (12/06) Practical Sequential Logic
Design(cont'd)
Week #12 ***** Final Exam(closed-book) *****************
Textbook :
No textbook, but a HW FPGA Board is
required for each student. The
textbook of CSE140 class is a good reference for this CSE140L class.
Computer needed for class(Window
PC, not Mac)
- Window PC is required. Mac does not
work since our CAD SW does run on Window, not on Mac.
- Student can use either
student's own PC or PCs on CSE3219
LAB room.
CSE3219 LAB Room
1. The CSE3219 LAB is
open 24 hours, 7 days a week. Access method to the lab will be announced for
students. The 3219LAB has Window PCs to be used by student. First read
CSE3219Lab General Policies
before using LAB.
2. CSE3219 LAB is a shared LAB with other classes and events.
Various hours/time slots are reserved for others frequently. Student
cannot use 3219 LAB room or LAB PCs when they are reserved for other
class or events.
If the 3219LAB room is reserved or
occupied by other event, tutor will meet students at the lobby area in front of the CSE3226. Student need to check the LAB Schedule
sheet posted on the LAB door or the event "CSE 3219" on Google Calendar
if available.
3. I have reserved 4-6pm M-Th for our class(however note
that it can be overridden
by more important or urgent event of department)
4. Where do you save your design data when using LAB PC? One
suggested option is, you bring & use your own USB drive.
Class ID(CID)
An unique 3-digit number called Class ID(CID) will be assigned to each student. Check
your TED account grade window to find your CID. The CID will be used throughout the course to
identify a student. CID starts from 001 to the number of students enrolled(e.g.,
249, etc.)
HW FPGA Board & CAD SW tools
1. HW FPGA Board(each
student should have one for the class.)
Altera Cyclone II FPGA Starter Development
Board(a.k.a
DE1 Board).
2. CAD SW(free download from Altera site --
see the link below)
Altera Quartus II Web Edition Software
v9.0 Service Pack 2 (works on Window 7/8,
Vista, XP) -- DO NOT use different version(e.g., later version).
-
If student uses CSE3219 LAB PC, it has SW installed already.
- If student uses his/her
own PC, download it from following Altera website, and
install it on your computer.
https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v90.jsp
The executable file name is "90sp2_quartus_free.exe" and the file size is about
1.31GB.
LAB Project(Working,
Submission and Demonstration)
Step 1. Working on LAB
project
- All LAB projects must be done by student
individually.
No group work is allowed.
- Discussion of information NOT directly related to the solution is
allowed among students(e.g., general discussion of Verilog, CAD SW, HW Kit, etc.).
However, sharing of
solution
or information directly related to the solution between
students is NOT allowed.
- It is highly
recommended to plan early and start the
project as early as possible for better chance of successful completion.
-
WARNING
against delaying Submission & Demonstration tasks until the last day. It is
NOT a
good idea to delay your work to the last day or last part of the project period. You
may have a pretty good
chance of missing due time.
Step 2. Submission
of Report & Design files to TED system
2.1 Student must submit a file to Ted system first before making a
demonstration. Each student should put following two files into a single ZIP file(file
name is "LxCyyy.zip"), and
submit it to TED system by
Submission Due date & time.
file#1) a PDF file of your LAB Report(file name is "ReportLxCyyy.pdf")
file#2) a ZIP file of your LAB Project design directory(file name is "ProjectLxCyyy.zip")
where, x=LAB
Number, yyy=your CID.
Example: For LAB1, student with CID#009
should submit L1C009.zip which contains
ReportL1C009.pdf and ProjectL1C009.zip.
Example: For LAB3, student with CID#196
should submit L3C196.zip which contains
ReportL3C196.pdf and ProjectL3C196.zip.
Notes: ---------
- DO NOT
CHANGE the contents of your LAB Report and
LAB Project Design AFTER you submit them.
- TED accepts your submission
only once per LAB. Resubmission is not
allowed by TED.
- No late
submission is allowed by TED.
-
If a student
misses submission
or submits an invalid, not-working or nonfunctioning
file(s), he/she will
receive zero(0) point for the
LAB regardless of Demonstration.
- No excuse for missing due
is accepted. For example, any SW, HW, Network failure, etc. is not an acceptable
excuse. Only
exception is a case that you were in an emergency which is
verified by
an official document
from Doctor, Police or UCSD. In such a case, student must contact instructor as soon as
possible.
2.2
Contents of LAB#4 Report------------------------------------------------------------
1) Use this
LAB4_Report_cover_page.docx (note: You
have to put the submission time stamp on hard-copy cover page
to demonstrate. You can copy & paste your submission time stamp from
[Review Submission History] window on Ted, e.g., Submission
( November 22, 2013 2:47:41 PM PST ). You don't put this
submission time stamp on zip file when submitting. )
2) Procedural description of work
done to complete the project
3) ***ONLY UPDATED PART*** of Verilog HDL
codes
4) ***ONLY UPDATED PART*** of State
Diagram of your design
5) A screen copy of Compilation
Report - Flow Summary(Clearly mark the Percentage(%) value of "Total logic
elements")
Contents of LAB#3 Report------------------------------------------------------------
1) Use this
LAB3_Report_cover_page.docx
2) Procedural description of work done to complete the project
3) Verilog HDL codes of your design
4) State Diagram of your design
5) A screen copy of Compilation Report - Flow Summary(Clearly mark the
Percentage(%) value of "Total logic elements")
Contents of LAB#2 Report------------------------------------------------------------
1) Use this LAB2_Report_cover_page.docx
2) Provide the followings in your
report.
a) Your work description(i.e., Describe what &
how you did in detail to complete the Parts in LAB#2)
b) A Flowchart drawing of your design(similar to a Flowchart when you
write a SW programming codes)
This is a graphical presentation of your LAB#2 work using the
flowchart format. Each student's presentation would be different depending
his/her work flow. There is, therefore, no standard solution or example. If you
are not familiar with the concept of flowchart, see
http://en.wikipedia.org/wiki/Flowchart
c) Complete Verilog Codes
d) Flow Summary in Compilation Report. Clearly mark the Percentage(%)
value of "Total logic elements"
e) Timing Analyzer Summary in Compilation Report. Clearly mark the
"Worst-case tco" row
Contents of LAB#1 Report------------------------------------------------------------
1) The Report must be written well and clean enough for grader to understand it
easily in order to receive any credit. It has no more than 10 pages
excluding cover page.
2) Use this LAB1_Report_cover_page.docx
3) You should provide the followings
in the report for LAB#1.
a) Your work description(i.e., Describe what &
how you did in detail to complete the Parts in LAB#1)
b) Schematic diagram
c) Functional simulation diagram (hint: similar to the one shown in the example diagram in
the LAB#1 Document)
d) Timing simulatio
diagrams. You must show at least one timing delay value on your waveform, just like
the one shown in the example diagram in the LAB#1 Document
e) Timing Analyzer Summary(hint: it is available after you compile
your design successfully)
Step 3. Demonstration
of your project to Demo Reviewer(instructor or tutor)
3.1. A student who
made a submission to TED is allowed to demonstrate
his/her design to Demo Reviewer(instructor or tutor) by
Demo
Due date &
time.
Notes: ---------
- DO NOT
CHANGE the contents of your LAB Report and
LAB Project Design AFTER you submit them.
- The LAB
Project design showing on demonstration
must be the same one
which was submitted to
TED. Otherwise it is regarded as
cheating and
zero(0) point
will be assigned to student.
- Demonstration is performed
during office
hours with first-come, first-served basis. No appointment for demonstration
will be made.
- No late Demo is allowed. No
defective malfunctioning DE1 board is allowed for Demo.
- If a student
misses Demonstration,
he/she will
get zero(0) point for the LAB
regardless of the submission. Only
exception is a case that you were in an emergency which is
verified by
an official document
from Doctor, Police or UCSD. In such a case, student must contact instructor as soon as
possible.
3.2 Student must bring a
hardcopy of LAB Report to
demo reviewer(instructor or
tutor) to start demonstration.
3.3 For demonstration, DE1 board should have been programmed with
your design using AS(Active Serial)
method, not JTAG method.
3.4 NO reprogramming of DE1
board is allowed during demonstration.
All the Parts of a LAB
project should be tested continuously without any interruption of reprogramming.
One exception may be LAB4(which may require reprogramming during demo.).
Grading
1. 100 points total:
Four LABs = 70 points(10 points for LAB#1, 20
points for each of remaining three, LAB#2-4)
Midterm exam
= 10 points
Final exam =
20
points.
2. LAB#1:
a) 5 points for Demonstration. The student score is determined by
tutor/instructor based on the quality of LAB Demo output result.
b) 5 points for a Report. The student score is determined by
tutor/instructor based on the quality of LAB Report.
LAB#2-4:
a) 15 points for Demonstration. The student score is determined by
tutor/instructor based on the quality of LAB Demo output result.
b) 5 points for a Report. The student score is determined by
tutor/instructor based on the quality of LAB Report.
3. NO Partial Credit Grading Policy(exception
can be made by instructor in special circumstance)
- Each LAB project
consists of
several Parts(for example, LAB#1 may have five Parts).
- You will get either
full score or
zero(0) on each
Part of
LAB. NO partial score is assigned to a Part.
- A full core is given only if
all required features of the Part are implemented and
demonstrated correctly. Otherwise zero(0) will be assigned.
- A
partial score, if given, is a clerical error and will be converted to zero(0)
point.
4. A plus(+) and minus(-) grading scheme will be used in the
final letter grade assignment(e.g., A+ A A-, B+ B B-, C+ C C-, etc.).
Academic Dishonesty & Student Conduct Policy
As student in this offering of CSE 140L, you are expected to know and abide by
the UCSD Policy on Integrity of Scholarship (as described in the
Student Conduct
Code in the UCSD General Catalog), the Jacobs School of Engineering
Student
Honor Code, and the course policy described here.
Any student violating UCSD's Academic Dishonesty or UCSD's Student Conduct
policies will earn an 'F' in the course and will be reported to their college
Dean for administrative processing. Committing acts that violate Student Conduct
policies that result in course disruption are cause for suspension or dismissal
from UCSD.
--------------------- The End ------------------