`timescale 1ns/1ps

`include "../../my_struct_s.sv"
   
module tb ();

      my_struct_s in, out;
      logic [$bits(my_struct_s)-1:0] in_flat, out_flat;
      assign in_flat = in;
      assign out = out_flat;
      
		initial begin                               // example testbench body code 
			 in.addr = 3;                       // example testbench body code
			 in.data = 2;                       // example testbench body code
		end                                         // example testbench body code

      core UUT(.my_struct_flat_i(in_flat), .my_struct_flat_o(out_flat));

endmodule