Fall 2012: CSE 140L
Digital Systems Laboratory
by
Dr. Choon Kim
CSE Dept., UCSD
News & Updates
29. 12/12/12: [Choon] Final exam is
under processing now. Student's grade will not be finalized until 12/18/12. The TED
Announcements section may have additional information regarding grade after
12/18/12.
28. 12/05/12: [Choon] Reminder:
Each student is responsible to check and make sure his/her
LAB1/2/3(which had been completed) scores are correct on TED by Fri. 12/07/12 if
not done yet, and LAB4 by Mon. 12/10/12.
27. 12/03/12: [Alvin] I have make up
tutor office hours tomorrow 12/04/12 Tue. 1 - 6pm.
26. 11/24/12: [Choon] FYI: Cypress is
hosting a PSoC World Virtual event that will take place Dec. 12-13. Click
Cypress_PSOC_World_Virtual_event for details.
25. 11/21/12: [Jonathan] I won't be able to
make my afternoon hours today, Wednesday (11/21/12). I will also be holding
extra hours the days before the last assignment is due.
24. 11/21/12: [Thinh] I will not be
available for lab tutor hours on today, Wednesday (11/21/12), due to sickness.
23 11/16/12: [Choon] LAB#4 Due:
Wed. 5pm 12/05/12
22. 11/15/12: [Alvin] I need to
reschedule my tutor hours on Friday 11/16 and Friday 11/30. I'll post the make
up hours later.
21. 11/12/12: [Choon]
LAB#3
(Reminder) As explained in the class, the
State Diagram generated from Quartus CAD SW is
NOT ACCEPTABLE
in our LAB Report.
20. 11/12/12: [Jonathan] I won't be
able to make my lab tutor hours tomorrow Tuesday (11/13/12). I will hold extra
hours on Wednesday.
19. 11/12/12: [Thinh] I will not be
available for lab tutor hours on Tuesday (11/13/12)
18 11/01/12: [Choon]
LAB#3 Due: Wed. 5pm 11/14/12 (note:
-2 points as a penalty if new cover page is NOT used in the LAB Report)
17. 10/29/12: [Alvin] My
tutoring time on Fri. has been changed from [11-1pm & 2-3pm] to [10-12pm &
2-3pm]
16. 10/22/12: [Choon] [Announcement]
Pop quizzes may be given to student
during any class(Discussion or Lecture) in this quarter without prior warning. The quiz score is a part of total
score(See Grading Section below). Pop quiz is taken
individually(i.e., not by group). Student who misses pop quiz will get
zero(0) quiz point (unless he/she was in an emergency
situation which is proved by an official document from Doctor, Police or UCSD).
15 10/18/12: [Choon]
LAB#2 a) Use updated LAB#2
Report contents located in Step1 Section.
b) Student can make demonstration to any reviewer(instructor or tutors).
14 10/16/12: [Choon]
LAB#2 Due: Wed. 5pm 10/31/12
13. 10/09/12: [Alvin] My
tutoring time schedule has been changed --- Check Tutors section
12. 10/08/12: [Choon]
All LABs: Initial condition
of DE1 board: Make sure that all SWs are in
down position & all KEYs are
not pressed when DE1 board power is turned on.
11. 10/07/12: [Choon] If you do not receive
GN(Group Number) in 48 hours after your email request to instructor & all
tutors, please forward your original email to me. I will help you on that.
10. 10/07/12: [Choon] Dr. Kim offers an
one-time extra office hour on 10/15/12 Monday 3-5pm and
10/17/12 Wednesday 3-5pm.
9. 10/07/12: [Choon] Dr. Kim's Tuesday
3-6pm office hour has been changed to 1-4pm(Check office hours list on Tutors
section).
8. 10/06/12: [Thinh]
LAB#1: One useful hint. See a
diagram in "Question about making input switch" thread on TED Discussion.
7. 10/05/12: [Choon] Lost&Found:
A DE1 Kit & 140TextBook found on WLH 2001 during
lecture today(Thank you student who reported me the found items!) ===>
The items claimed & returned to the owner.
6. 10/03/12: [Jonathan] My
tutoring time schedule has been changed --- Check Tutors section
5. 10/01/12: [Choon] Web Browser
issue: If chrome gives you a problem on Window(e.g., fail
downloading a file on our slide, etc) try other ones, like firefox
or IE. I and all LAB PCs have been using firefox with Window 7
accessing all the materials in this class and never had a problem in the past.
Let me & tutors know if all three browsers fail on your Window 7 machine(I
hardly believe it, but such thing can happen.). You need to use LAB
PC in such a case.
4. 10/01/12: [Choon] Reminder:
As specified in Computer for class and CAD SW sections, our class CAD program &
various files are all based on Window. That means Apple Mac user should find a
way to use Window. For example, using 3219LAB PCs or install Window on Mac, etc.
3. 10/01/12: [Choon]
LAB#1: Group whose number ends
with 0, 4 or 9 must demonstrate only to instructor(GN=x0, x4, x9). Other group
can demonstrate to any reviewer (i.e., instructor or tutor).
2. 09/30/12: [Choon] 3219LAB access code is
available on TED, My Announcements section.
Following time is reserved for other classes(i.e., you should not use LAB during
this period)
7:30pm - 10:30pm every day; 1pm - 3pm every Wed.; 1:30pm
- 4:30pm every Fri. More time period may be reserved later.
Following time is reserved for our CSE140L class(i.e., you may use LAB
exclusively during this period)
3pm - 6pm MTThF; 3pm - 4pm W
Check LAB time schedule posted on the LAB door.
1. 09/28/12: [Choon] Class starts at
12pm.
LAB#1 Due: Wed. 5pm 10/17/12
Message from Instructor
Welcome to CSE140L class! The knowledge & skills that you will learn from
this class can be very helpful in your engineering career in the future. The
class LAB projects you will do can be also fun to enjoy. I wish all of students
a good luck in my class.
Course Description
Implementation with computer-aided design(CAD) tools for combinational logic
minimization and state machine synthesis. Hardware construction of a small
digital system. See http://www.cs.ucsd.edu/cse140L.
Websites
http://cseweb.ucsd.edu/classes/fa12/cse140L-a/ For Syllabus,
News & Updates, Lecture notes, LAB
assignments, etc.
https://ted.ucsd.edu/webapps/login/ For Submitting LABReport, Checking grade,
Discussions among students , etc.
Instructor
Dr. Choon Kim, office: CSE3218, office phone: 858-246-0320, email:
chk034@eng.ucsd.edu
Office hours(see tutor section below)
Course Information Sources
1. This course webpage and
instructor are
only valid information sources for any
course-related issues such as LAB Projects, Reports, Grading, Exam, or any other
course-related issues.
If student has any specific
question which is not answered on this course webpage, he/she should ask
instructor about it. Therefore an excuse based on any source other than above two is not accepted by
instructor. For example, an excuse like "A tutor said this...", "A friend of
mine said that...", "I heard it from somebody who took this class before...",
etc. is not accepted.
2. Just in case when an information from instructor is inconsistent with
the information on course web page, student must discuss with instructor about
it in order to get a correct information.
3. Student is required to check this webpage at least once a day.
Tutors
Rules about tutors:
Student, not tutor, is responsible for completing project successfully. Any
information from tutor must be treated by student as an unconfirmed or
unverified reference. Student is responsible to check & confirm the correctness
and the validity of information obtained from tutor. Therefore any excuse by
student based on tutor(for example, "Tutor said this or that....", etc.) is
not
accepted by instructor.
Location: CSE3219LAB (If 3219 is reserved or
occupied by other event, tutor will meet at the lobby in front of the CSE3226)
Alvin Chen
alc012@ucsd.edu M 11-1, 4-5
W 12-1, 4-5
F 10-12, 2-3
Jonathan Masehi-lano jmasehil@ucsd.edu
M 9:45-11:45 T 9:30-10:30
W 9:45-10:45, 3-4 Th 9:30-10:30 F 9:45-11:45
Thinh Nguyen
thn024@ucsd.edu
T 3:30-5:30 W 11-5
Gabriel M Alsheikh
galsheik@ucsd.edu
M 1-3
T 1-3
Th 10-2
Instructor(Dr. Kim)
T 1-4 Th 3-6
Lecture & Discussion Time Schedule(Confirm
with
Tritonlink.
If different, Tritonlink is correct always):
Discussion: 12 - 12:50pm Fri at CENTR 115
Lecture: 01 - 01:50pm Fri at WLH 2001
Final Exam(Closed-book): 11:30am- 02:29pm, Mon. 12/10/2012
***CAUTION: Student is required to attend all the lectures & discussions. If a student misses a class, he/she is responsible
to recover all the missing information as soon as possible.
Week #1 Introduction to course, LAB HW, SW, doc information, CAD Process, LAB#1
assignment
Week #2 Discussion Intro. to Logic Design,
Week #3 Comb. Logic, Introduction to Verilog HDL,
Week #4 Intro. to Sequential Circuit Design, Verilog HDL(cont'd),
LAB#2
assignment
Week #5 Sequential Circuit Design(cont'd), FSM,
Week #6 FSM(cont'd), LAB#3 assignment
Week #7 FSM(cont'd),
Week #8 Practical Sequential Logic Design,
LAB#4 assignment
Week #9 Practical Sequential Logic Design(cont'd)
Week #10 Practical Sequential Logic Design(cont'd)
Week #11 Practical Sequential Logic Design(cont'd)
Textbook : Lab Handout
Computer for class(Window PC) --- LAB PC or
Student's own PC?
Student can use either of them for this class work.
LAB Room-- CSE3219
*** Note: If student uses his/her own PC, he/she does not need to use 3219LAB PCs.
1. The CSE3219 LAB is
open 24 hours, 7 days a week. Student may use a student ID card to access the
LAB. The 3219LAB has Window PCs to be used by student. First read
CSE3219Lab General Policies
before using LAB.
2. CSE3219 LAB is a shared LAB with other classes and events.
Various hours/time slots are reserved for others frequently. Student
cannot use 3219 LAB room or LAB PCs when they are reserved for other
class or events. Student need to check the LAB Schedule
sheet posted on the LAB door or the event "CSE 3219" on Google Calendar
if available.
3. When using LAB PC, where do you save your design data? First suggested option
is you bring & use your own USB drive. The other option may be you use a disk
space reserved for your account if possible.
Grouping & Group Number
1. Two students make one group, working together for
LAB projects throughout the course(Note: Final Exam
is taken individually)
Group members share DE1 kit, work together, submit one Report, and make one LAB
Demonstration to instructor or tutor. Two members will get a same score for each
LAB project.
2. Student is responsible for finding his/her group partner.
The sooner the better, but it must be done no later than 10/08/12. When done,
student should send instructor and all tutors an email with a list of two names
of your group members. Then your group number will be assigned to you.
3. Group does NOT mean that work is divided into
two members. Each member of a group is 100% responsible for
all the works needed to complete LAB project successfully regardless of his/her partner.
For an example, a member student is 100% responsible to complete the project
even though his/her partner becomes inactive or unavailable due to any event
such as drop/withdraw the class, a car accident, sickness, etc.
HW kit("DE1") & CAD SW("Quartus II") tools
1. HW Kit(need to purchase):
Altera Cyclone II FPGA Starter Development Kit(a.k.a DE1 Kit).
The kit should be purchased by student. UCSD Book store has kits(but it can be
purchased from any electronic store if necessary). Note that a group shares a kit(See below
"Grouping" section to learn about group).
2. CAD SW(free download from Altera site):
Altera Quartus II Web Edition Software v9.0 Service Pack 2 (works on Window 7,
Vista, XP) -- DO NOT use different version(e.g., later version).
The CSE3219 LAB PC has SW installed and is ready to be used. If student plans
to use his/her own computer, download it from following Altera website, and
install it on your computer.
https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v90.jsp
The executable file name is "90sp2_quartus_free.exe" and the file size is about
1.31GB.
LAB Report Submission & Demonstration
*** CAUTION: Try your best not to delay this task to
the last day. Due to congestion on last day, you may have a good
chance to miss the project due and get a zero(0) point.
Step 1: (Submitting LAB Report to TED)
-------------------------------------------------------------------
1. First, a group submits following two files to TED before demonstration.
a) the final version of LAB Report file in PDF format, and
b) the final version of LAB project design directory in ZIP format(i.e., all your LAB Project design
files)
Notes:
- TED accepts your submission
only once per LAB. Resubmission is not
accepted by TED.
- TED does not accept submission after due.
- If a group
misses due time because of an emergency situation which is proved by an official document
from Doctor, Police or UCSD, group must contact & discuss with instructor as soon as
possible.
2. The LAB Report file name is LxGyy.pdf where x=LAB
number, yy=your group number.
For example, L1G09.pdf is a LAB Report of LAB#1 created by Group#9.
In the same way, the project directory ZIP file name is LxGyy.zip where x=LAB number, yy=your group
number.
For example, L1G09.zip is a zip of LAB#1 project directory created by Group#9.
3. Contents of LAB#3 and LAB#4 Report
1) Use this
LAB_Report_cover_page.docx
(note: -2 points as a penalty if new cover page is NOT used in the LAB Report)
2) Procedural description of group's work done to complete the project.
3) Verilog HDL codes of your design(For LAB#4, only updated parts are needed)
4) State Diagram of your design
5) A screen copy of Compilation
Report - Flow Summary(Clearly mark the Percentage(%) value of "Total logic
elements")
Contents of LAB#2 Report (updated from LAB#1 Report below)
1) Use this
LAB_Report_cover_page.docx
2) Procedural description of group's work done to complete the project.
3) Verilog HDL codes of your design
4) A screen copy of Compilation
Report - Flow Summary(Clearly mark the Percentage(%) value of "Total logic
elements")
Contents of LAB#1 Report
1) The Report should be well organized and clearly written. It has no more than 15 pages
excluding cover page.
2) Use this LAB_Report_cover_page.docx
3) Procedural description of group's work done to complete the project.
4) Schematic diagram or HDL codes of your design
5) Functional simulation waveform
output diagrams
6) Timing simulation waveform output
diagrams
7) Timing Analyzer Summary
8) Additional information if requested by instructor
Step 2: (Personal demonstration to instructor or tutor)
------------------------------------------------------
1. After completion of Step 1, a group can make demonstration to Demo
Reviewer(instructor or tutor) by LAB due.
Demo is performed during
office hours with first-come, first-served basis. No appointment for demonstration
will be made.
*** CAUTION: NO updating your design is allowed after TED
submission. The LAB design showing on demonstration
must be the same one
which was submitted to
TED. Otherwise it is regarded as
cheating AND zero(0) point will be assigned to the group.
2. Group submits a hardcopy of LAB Report to Demo Reviewer(instructor or
tutor) before demonstration starts.
3. Before demonstration, DE1 kit is programmed with
complete LAB design using AS(Active Serial)
method. No recompilation/reprogramming of DE1 kit is allowed during demonstration.
All the Parts should be tested continuously without any interruption of recompilation or reprogramming.
4. Both members of group must be present at demonstration(unless group gets an
approval from instructor before demonstration).
5. No demonstration is accepted after LAB due.
Zero(0) point will be assigned to the group who misses LAB due.
(If a group misses LAB due because of an emergency situation which
is proved by an official document from Doctor, Police or UCSD, group must contact
& discuss with instructor as soon as
possible.)
Grading
1. 100 points total:
Four LABs = 80 points(20 points per LAB including Pop
Quizzes score if given), Final Exam = 20
points.
2. Each LAB has
a) 15 points for LAB Demonstration. The student score is determined by
tutor/instructor based on the quality of LAB output result.
b) 5 points for a LAB Report. The student score is determined by
tutor/instructor based on the quality of LAB Report.
c) If pop
quizzes are given, some of above LAB Demo or Report points will be
assigned to the quiz score. Since a pop quiz is taken individually, LAB partners
may get a different LAB score depending on the pop quiz score.
3. A plus(+) and minus(-) grading scheme will be used in the
final letter grade assignment(e.g., A+ A A-, B+ B B-, C+ C C-, etc.).
4. No Partial Credit Grading Policy on each Part of
LAB
Each LAB project may have
several Parts(e.g., five Parts in LAB#1). You will get either
full score or nothing(=zero) on each part of
LAB. A full core is given only if all required features of the Part are implemented and
demonstrated correctly. Otherwise zero(0) score is assigned.
Any partial score, if given on any Part, is an error and will be converted to
zero(0) point.
Academic Dishonesty & Student Conduct Policy
As student in this offering of CSE 140L, you are expected to know and abide by
the UCSD Policy on Integrity of Scholarship (as described in the
Student Conduct
Code in the UCSD General Catalog), the Jacobs School of Engineering
Student
Honor Code, and the course policy described here.
Any student violating UCSD's Academic Dishonesty or UCSD's Student Conduct
policies will earn an 'F' in the course and will be reported to their college
Dean for administrative processing. Committing acts that violate Student Conduct
policies that result in course disruption are cause for suspension or dismissal
from UCSD.
------------------------------- The End -------------------------------