Xilinx tips and tricks

This webpage describes some common problems that appear with Xilinx tools as well as their respective solutions. In case you have some more problems and fixes to contribute please email the instructor or the TA.

Problem1: ISE does not start

Solution:

  • Clean up the project files. In order to do that go to "Project>Cleanup Project Files" as instructed in the following picture and in pop-up click ok. Note that this will delete those files instead of just removing them from your project.

  • Open the task manager, kill redundant ISE processes. Press Alt-Ctrl-Del and look in the processes tab for "ise.exe". If there are more than one instances the chances are that something is wrong. Kill one of them.


    • Problem2: Whenever I try to add a file to the project, I get a weird error.

    Solution: Make sure there are no spaces in the project path and the path of the file you want to add (Desktop is a symbolic link to C:\Documents and Settings\user_name\Desktop and therefore has spaces; avoid it). Xilinx is notorious for not being able to parse paths containing spaces. So don't ask for trouble.


    Problem3: Whenever I start ISE simulator the clock is set to high impedance (Z) even if I have properly set it up.

    Solution: It seems like you are simulating the wrong file. Make sure that the testbench is selected in your sources window and not the UUT (unit under test).


    Problem4: My simulation starts correctly but I can not observe the internal signals of my UUT?

    Solution: To add the signals you need choose the Sim Instances tab in the sources window. Select the UUT and in the processes window select the Sim Objects. Then right click on the signals of your choice and click "Add to Waveform". Altenatively you can drag and drop the signals to the Simulation/Waveform window. If you want to select all the signals of a module right click on a module in the Sim Instances tab and click "Add to the Waveform".


    Problem5: Place and Route fails with ERROR:Par:228 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint.

    Solution: The timing constraints you have set are too tight and impossible to meet. You need either to set higher period target in your timing constraints.


    Problem6: Random Xilinx weirdness. While you work Xilinx reports an error and dies immediately.

    Solution: Many things could have gone wrong. The most common one is that the tool has corrupted your project files. In this case, it is better to give up on your current project and start a new one from the beginning. Open a previous project (.ise file) which you know to be working and start a new project by adding the .v files you used. You should always prefer to add and copy the sources of the files into your project ( "Add Copy of Source" over "Add source" when you right click on the project ).