CSE 140 Fall 2008 

(Mon/Wed: 3:30 - 4:50pm, EBU3B 2154)

Instructor:

Alex Orailoglu, alex@cs.ucsd.edu

Office Hours:
Mondays 2:30 – 3:30 PM and Wednesdays 1:30 – 2:30 PM;

EBU3B 3134

Teaching Assistants

Mingjing Chen

mjchen@cs.ucsd.edu

Office Hours

Tuesdays 4:00 – 5:00 PM and Wednesdays 11:00 AM – 12:00 noon and 8:00 – 9:30 PM; EBU3B B240A

Discussion Section: Tuesdays 11:00 AM - 12:20 PM ; WLH 2111

Text Book: Principles of Digital Design, by Daniel D. Gajski, Prentice Hall, 1997. Available in the reserve section of the undergraduate library.

Mid-Term 1: October 22, 2008
Mid-Term 2: November 12, 2008
Final: 12/12/2008, 3:00 - 5:59 PM

Announcements:
*Please check back frequently to see the updated announcements.

*Mingjing will give the lecture on Monday (10/6) and move the discussion section to Wednesday (10/8) lecture time. No discussion section on Tuesday (10/7)

*Alex will give a make-up lecture on Tuesday (10/14) using the discussion section time.

*Mingjing will give a review session for the second midterm on Tuesday (11/11) in EBU3B 2154

*Section 3.10 (pp.95-108) of the textbook will not be covered. You can skip it when preparing for the test.

*Alex will hold office hours next week on Monday (Dec. 8) regular time but not on Wednesday due to the conflict of exam time.

*Mingjing will hold office hours next week on Tuesday afternoon (Dec. 9)and Wednesday evening (Dec. 10) regular time but not on Wednesday noon due to the conflict of exam time.

*Mingjing will give a review session for the final on Sunday (Dec. 7) 1:00-2:00pm in EBU3B 2154

*Please read the tutorial on how to turn your homework
 Link to WebCT: http://webct.ucsd.edu/

Homeworks:

• HW1 Due Oct. 21, 2008 at 9:00am

• HW2 Due Nov. 11, 2008 at 9:00am

• HW3 Due Dec. 5, 2008 at 9:00am

Errors in the text book:

1.        Fig 2.10 part C: excess 1032 should be excess 1023

2.        Fig. 3.3: xi, yi -> si delay should be 7.6, NOT 7.2

3.        Fig. 3.4 xi, yi -> ci+1 delay should be 3.2, NOT 4.2

4.        Fig. 3.5 AOI 3-wide, 2-inputs, marked delay on the schematic should be 2.2 not 2.0 Consequently all 4.4 ns delay paths in summary should also be 4.6

5.        Page 144, QM tables, subcubes (8,9) should be 1 0 0 _ instead of _ 0 0 1; subcubes (9,13) should be 1 _ 0 1 instead of 1 0 _ 1; subcubes (13,15) should be 1 1 _ 1 instead of 1 _ 1 1.  Figure 4.18 (d), the prime implicant expression of P2 should be wx'y' instead of x'y'z; the prime implicant expression of P4 should be wy'z instead of wx'z; the prime implicant expression of P6 should be wxz instead of wyz. Corresponding changes of the expressions should also be made in the PI list, EPI list and Cover lists in Figure 4.18(e), as are done in your Chapter 4 handout

6.        Table 5.2: The delays marked as x0,y0 are actually from any x,y input, the worst case delay actually comes from x3,y3 because the generate signal for the CLA block does not depend on the propagate signal of x0,y0

7.        Table 5.2: x0,y0 -> c8 delay should be 15.8, NOT 16.2

8.        Table 5.2: x0,y0 -> c12 delay should be 16.6, NOT 17