cse240a Project 2: Prefetching competition

Due: 12 noon, December 4


12/03/2007 - Version 1.5 of the source code is now up. It's last minute so don't worry if you have already submitted (your grade won't be adversely affected).
11/28/2007 - Version 1.4 of the source code is now available here and on the webboard. See the changelog for a description of the changes.
11/26/2007 - The source code has been updated to version 1.3. Please make sure you have the latest version.


In this project you will be working to implement a hardware prefectcher. You will be given a basic cache simulator with an interface to a prefetcher. Your task will be to implement the prefetcher interface with a prefetching algorithm of your own choice. The effectiveness of your prefetcher will be tested against a baseline prefetcher. You will also compete against your fellow classmates for amazing awards and prizes!

The slides from the in-class description of the project are here.

Cache Configuration:

Your prefetcher will work in the context of a well-defined memory hierarchy. The memory system is already implemented (in C++), and can be downloaded here: proj2-source.tar.gz. The Data Cache has the following stats:

A L2 cache (data only) has the following stats: Because it is fully pipelined, it is possible to issue 1 request (either from the data cache or the prefetcher) to the L2 cache per cycle.
Main memory has an access time of 50 cycles and is not pipelined (i.e. only one request can be handled at a time). Accesses to main memory are held in a FIFO queue with 10 entries. If the FIFO fills up, the L2 will no longer accept requests.

Prefetcher Interface:

Your main task in this project will be to implement a prefetcher using the given prefetching interface. The system controller provides information about all loads and stores that are issued by the CPU. The information that is provided includes the effective memory address, PC of the memory instruction, and whether the instruction was a load or a store. You may use this information in any way that you see fit. During all cycles where the CPU is not issuing a request to the L2 cache, the system controller will query the prefetcher for any memory requests that it may have. While your prefetcher may have many requests queued internally, the system will service a maximum of 1 per cycle. After the prefetching request has been satisfied (either from the L2 or main memory), it will be placed in the Data Cache.

The file prefetcher.h pre-defines four functions that must be implemented:

The prefetcher is called only from the main.C file.

While you are free to examine all parts of the provided memory system, the only modifications you should make is to the prefetching interface contained in the files prefetcher.h and prefetcher.C. The only source code you will be submitting are these two files.

To aid in your understanding of the prefetcher interface, we have provided a sample prefetcher implementation. This simple prefetcher waits for misses on the D-cache and then tries to prefetch the next block in memory. You can download the sample here: sample-pf.tar.gz.

Constraints on Prefetcher:

In addition to the constraint that only a single request can be serviced per cycle, you will have one further constraint: the amount of state saved in the prefetcher. The amount of state saved in the prefetcher may not exceed 4KB. Your source code must clearly indicate which variables are used as state. Furthermore, you will need to provide a detailed accounting in your project report of how much state is kept.

Cache Simulation:

The memory hierarchy will be simulated using trace files generated by the Pin binary instrumentation tool. Each line in the trace file refers to a memory access and includes the following four pieces on information:

While you will not be required to generate trace files for this project, you may wish to generate them to more thoroughly test your prefetcher's performance. A Pintool, named memtracer2, that will produce trace files of the format required for this project is available here: memtracer2.tar.gz. It's operation is the same as the memtracer tool provided as part of Project 1.

Simulation Statistics

The memory system provided will output several statistics about the performance of the system. They will help you understand how your prefetcher is performing and why. The stats include:

These stats will be placed in the file mem.trace.out, where mem.trace was the input file used. You may wish to extend the simulator to collect more stats. This is not required, and your prefetcher should not depend on these modifications.

Average Memory Access Time will be used for comparisons of your prefetcher to the baseline and your colleagues' prefetchers. For your report, you should test your prefetcher on traces available here: proj2-traces.tar.gz.


You should feel free to discuss the project with others in the class including sharing detailed performance results of your predictor (I changed my mind about this after class on Tuesday). Sharing code is expressly forbidden.

Prefetcher starting points

Here are some papers to get you thinking about different approaches to prefetching. You are not required to choose an algorithm from these papers, but they can provide some useful starting thoughts. Their bibliographies will provide pointer to other papers on the topic.


Your grade for the project will be based on your write up the prefetcher you implemented. The performance of your prefetcher is less important than your discussion of how the prefetcher works and why it performs the way it does.

Fabulous PRIZES!!!

The authors of the three top prefetcher (as measured by total run time) will receiver prizes. The prizes will be awarded in class on December 6th.


Project 2 Report

Your report for project 2 will consist of the following sections:

  • Description of Prefetcher - One or two paragraphs describing the prefetching algorithm that you are using. If your prefetcher is based on an existing design, you must explicitly state the original source. While you are free to implement existing designs, failure to provide a citation will result in you receiving no credit for the project. Your description should include the rationale for the design, supported, where appropriate data evaluating "teaks" or changes you made to improve performance.
  • State Accounting - How much state your prefetcher uses as well as a detailed description of how and where the state is used. For example, if you have a prediction table, you should list its size as well as its layout.
  • AMAT Graph - A bar chart showing the average memory access time (AMAT) of your prefetcher on the provided traces.
Your report should be in PDF format and have the following name: lastname-firstname-cse240a-fa07-proj2.pdf

Source Code

You only need to submit two source code files: prefetcher.h and prefetcher.C. Your prefetcher should be able to compile with the unmodified memory system that has been provided. The given system is written in C++ so your code should compile with the g++ command on the APE lab computers. This file should contain your name as well as your PID at the top.

Electronic Submission

Please submit the report and source code file via e-mail to Sat.

Due: 12 noon, December 4