cse240a Project 2: Prefetching competition

Due: 12 noon, December 4

Announcements:

12/03/2007 - Version 1.5 of the source code is now up. It's last minute so don't worry if you have already submitted (your grade won't be adversely affected).
11/28/2007 - Version 1.4 of the source code is now available here and on the webboard. See the changelog for a description of the changes.
11/26/2007 - The source code has been updated to version 1.3. Please make sure you have the latest version.

Introduction:

In this project you will be working to implement a hardware prefectcher. You will be given a basic cache simulator with an interface to a prefetcher. Your task will be to implement the prefetcher interface with a prefetching algorithm of your own choice. The effectiveness of your prefetcher will be tested against a baseline prefetcher. You will also compete against your fellow classmates for amazing awards and prizes!

The slides from the in-class description of the project are here.

Cache Configuration:

Your prefetcher will work in the context of a well-defined memory hierarchy. The memory system is already implemented (in C++), and can be downloaded here: proj2-source.tar.gz. The Data Cache has the following stats:

• 32KB Size
• 2-way Set Associative
• 16 byte line size
• write-through
• no-write-allocate
• 1 cycle hit time
• 10 entry write-buffer

• 256KB Size
• 8-way set associative
• 32 byte line size
• write-back
• write-allocate
• 20 cycle access time (fully pipelined)

Prefetcher Interface:

Your main task in this project will be to implement a prefetcher using the given prefetching interface. The system controller provides information about all loads and stores that are issued by the CPU. The information that is provided includes the effective memory address, PC of the memory instruction, and whether the instruction was a load or a store. You may use this information in any way that you see fit. During all cycles where the CPU is not issuing a request to the L2 cache, the system controller will query the prefetcher for any memory requests that it may have. While your prefetcher may have many requests queued internally, the system will service a maximum of 1 per cycle. After the prefetching request has been satisfied (either from the L2 or main memory), it will be placed in the Data Cache.

The file prefetcher.h pre-defines four functions that must be implemented:

• bool hasRequest(u_int32_t cycle) - Value returned indicates whether there is a request waiting from the prefetcher. This function is used as a gate before getRequest() is called.
• Request getRequest(u_int32_t cycle) - Returns a request to be sent to the L2 cache. Only the addr field of the Request struct will be used.
• void CompleteRequest(u_int32_t cycle) - This function is called as soon as the last request is successfully sent to the L2 cache.
• void cpuRequest(Request req) - This function is called after a CPU request is handled. The request gives the addr, pc, cycle it was issued, and whether it was a hit or miss in the D cache.

While you are free to examine all parts of the provided memory system, the only modifications you should make is to the prefetching interface contained in the files prefetcher.h and prefetcher.C. The only source code you will be submitting are these two files.

To aid in your understanding of the prefetcher interface, we have provided a sample prefetcher implementation. This simple prefetcher waits for misses on the D-cache and then tries to prefetch the next block in memory. You can download the sample here: sample-pf.tar.gz.

Constraints on Prefetcher:

In addition to the constraint that only a single request can be serviced per cycle, you will have one further constraint: the amount of state saved in the prefetcher. The amount of state saved in the prefetcher may not exceed 4KB. Your source code must clearly indicate which variables are used as state. Furthermore, you will need to provide a detailed accounting in your project report of how much state is kept.

Cache Simulation:

The memory hierarchy will be simulated using trace files generated by the Pin binary instrumentation tool. Each line in the trace file refers to a memory access and includes the following four pieces on information:

• Whether the instruction is a load or store
• PC of memory instruction (32 bits)
• Effective Memory Address (32 bits)
• Number of non-memory ops since the last memory operation

Simulation Statistics

The memory system provided will output several statistics about the performance of the system. They will help you understand how your prefetcher is performing and why. The stats include:

• Total Run Time
• D-Cache Total Hit Rate
• L2 Total Hit Rate
• Average Memory Access Time
• Average Memory Queue Length
• D-Cache-to-L2 bandwidth utilization
• Memory bandwidth utilization

Average Memory Access Time will be used for comparisons of your prefetcher to the baseline and your colleagues' prefetchers. For your report, you should test your prefetcher on traces available here: proj2-traces.tar.gz.

Collaboration

You should feel free to discuss the project with others in the class including sharing detailed performance results of your predictor (I changed my mind about this after class on Tuesday). Sharing code is expressly forbidden.

Prefetcher starting points

Here are some papers to get you thinking about different approaches to prefetching. You are not required to choose an algorithm from these papers, but they can provide some useful starting thoughts. Their bibliographies will provide pointer to other papers on the topic.

• Spectral prefetcher: An effective mechanism for L2 cache prefetching
• A stateless, content-directed data prefetching mechanism
• Prefetching using Markov predictors
• Memory Prefetching Using Adaptive Stream Detection
• Reducing memory latency via non-blocking and prefetching caches

Evaluation

Your grade for the project will be based on your write up the prefetcher you implemented. The performance of your prefetcher is less important than your discussion of how the prefetcher works and why it performs the way it does.

Fabulous PRIZES!!!

The authors of the three top prefetcher (as measured by total run time) will receiver prizes. The prizes will be awarded in class on December 6th.