CSE 140 Components and Design Techniques for Digital Systems
Announcement: Due to campus closure, midterm is postponed to next Tuesday (Oct 30th) in class.

Class Tu & Thu 11:00am - 12:20pm, WLH 2111

Course The objective of this course is to introduce digital components and digital systems designs

Textbook Required. "Contemporary Logic Design", Randy H. Katz & Gaetano Borriello, 2nd edition, 2005, Prentice Hall

Instructor Isaac Chu, UCSD Guest Lecturer, Systems Architect
ichu@ece.ucsd.edu
Office hours: @ EBU3b 2106 (starts on 2nd week)
Tuesday, Thursday 9:30-11am
T.A. Yatharth Saraf (ysaraf@ucsd.edu)
Office hours: (starts on 2nd week)
Monday 2-4pm @ EBU3b B250A, Wednesday 9am-11am @ EBU3b B260A (please note the change).
Wenjing Rao (wrao@ucsd.edu)
Office hours: @ EBU3b B240A (starts on 2nd week)
Wednesday 5-7pm, Friday 10am-12pm

Discussion section also starts on the 2nd week.

Course Plan
week # Monday Tuesday Wednesday Thursday Friday
0       9/27
Switch Networks
CMOS
Intro to Boolean Algebra
  
1   10/2
Boolean Algebra
K-Map
   10/4
K-Map cont.
Product of Sum
Multi-level logic
  
2   10/9
Nand-Nand
Hazards
   10/11
MUX
DEMUX 		 
3   10/16
PLA & PAL
   10/18
Memory types
Midterm Review 		 
4   10/23
Midterm 1
Assgn #1 Due 		  10/25
Memory Element
Latches
D-Flip Flop
  
5   10/30
Registers
Counters
   11/1
Flip Flops Variations
  
6   11/6
Counter variations
Finite State Machines
   11/8
More FSM
  
7   11/13
FSM Circuit Issues
   11/15
More FSM examples
Midterm review 		 
8   11/20
Midterm 2
Assgn #2 Due 		  11/22
(Thanksgiving)
9   11/27
State reduction 		  11/29
State reduction cont.
State assignment
  
10   12/4
State assignment cont.
Case studies
   12/6
More example
Final review
  
final     12/12
11:30am - 140 final
Assgn #3 Due 		   

Grading 15 % : Assignments
25 % : Midterm 1
25 % : Midterm 2
35 % : Final Exam
Assignments Assignment #1 :
Ch1 (1, 2)
Ch2 (4, 17, 26)
Ch3 (12-nand gates only, 18-abc)
Ch4 (13-abc)

Assignment #2 :
Ch6 (12, 13, 14, 15, 16)
Ch7 (1, 20)

Assignment #3 :
Ch8 (4, 6)