Project 2: Computer Architecture Research Survey

Due: Tuesday, November 21 at Noon.

For this project, you will be choosing one area of computer architecture research and, starting with one of the important papers in that area, doing a survey of work in that area.

Below is a list of computer architecture research areas. Under each area is listed one of the important papers from this area. Your task is to choose one of these areas and write a report on the paper and its associated area. Your report will consist of the following aspects:

1. Introduction - Provide the context in which the work was done and the significance of the results. Why may this paper be considered seminal?
2. Synopsis - Elaborate on the key contributions of the paper. Explain any architectural and methodological mechanisms that are proposed or evaluated in the paper.
3. Analysis and Related Work - Compare this work to other work in this area that preceded and followed the paper. Discuss what open problem(s) the paper addressed, any open problem(s) it failed to address, and any new problems that it created. Analyze the work, and suggested future areas of exploration.
4. Citations - This contains bibliography entries for the papers that are cited in the above sections. You can use the bibliography of the target paper to figure out the papers to read for related work and to cite. Do not blindly copy the bibliography unless you have verified the relevance of the paper. You can also look for highly-cited successor papers that cite this paper using Google Scholar (scholar.google.com).

Your report should be 6 pages (not including citations), broken down like this:

1. Introduction - 1 page
2. Synopsis - 3 to 3.5 pages
3. Analysis and Related Work - 1.5 to 2 pages

Your report should be formatted using LaTeX and should use a 2-column layout with 1 margins (on all sides) and 10pt font. A LaTeX template can be found here, while a sample BibTex file can be found here.

It is STRONGLY RECOMMENDED that you work in groups of 2 on all parts of the project. If you do work with a partner, you should only submit 1 writeup per group. You are free to consult any resources available to you (Google Scholar, CiteSeer, IEEE Explore, ACM Digital Library, etc) but it is important that you cite whatever sources you use.

If there is an area not listed here that you would like to survey, please consult the professor or TA to get approval.

Please submit your writeup to Sat, either in person or via his mailbox in the grad student mailroom.

The following is a list of research areas that you are to choose from. Each area has one paper listed as its "important" paper. The papers can easily be located with the use of Google Scholar (although you might need to be on the UCSD network to access them through IEEE or ACM).

1. Tiled Architectures:
   • Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Paul Johnson, Jae-Wook Lee, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, Anant Agarwal, "The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs," IEEE Micro, vol. 22, no. 2, pp. 25-35, Mar/Apr, 2002.
2. Multicore Processors:
   • Olukotun, K., Nayfeh, B. A., Hammond, L., Wilson, K., and Chang, K. 1996. "The case for a single-chip multiprocessor." In Proceedings of the Seventh international Conference on Architectural Support For Programming Languages and Operating Systems (Cambridge, Massachusetts, United States, October 01 - 04, 1996). ASPLOS-VII. ACM Press, New York, NY, 2-11.
3. Interconnection Networks:
   • Jose Duato, "A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 06, no. 10, pp. 1055-1067, Oct., 1995.
4. Transactional Memory:
   • Ananian, C.S.; Asanovic, K.; Kuszmaul, B.C.; Leiserson, C.E.; Lie, S., "Unbounded transactional memory," High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on , vol., no.pp. 316- 327, 12-16 Feb. 2005
5. Technology Trends:
   • V. Agarwal, M.S. Hrishikesh, S. W. Keckler, and D. Burger. "Clock rate versus ipc: The end of the road for conventional microarchitectures." In the 27th Annual International Symposium on Computer Architecture, May 2000.
6. Fault-Tolerant/Reliable Computing:
   • Todd M. Austin, "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design," micro, p. 196, 32nd Annual International Symposium on Microarchitecture, 1999.
7. Low-Power Design:
   • Brooks, D.M.; Bose, P.; Schuster, S.E.; Jacobson, H.; Kudva, P.N.; Buyuktosunoglu, A.; Wellman, J.; Zyuban, V.; Gupta, M.; Cook, P.W., "Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors," Micro, IEEE , vol.20, no.6pp.26-44, Nov/Dec 2000
8. Vector Processors:
   • Ronny Krashinsky, Christopher Batten, Mark Hampton, Steven Gerding, Brian Pharris, Jared Casper, and Krste Asanovic, "The Vector-Thread Architecture", 31st International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004
9. Reconfigurable Processors:
   • J.R. Hauser, J. Wawrzynek, "Garp: a MIPS processor with a reconfigurable coprocessor," fccm, p. 12, 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), 1997.
10. High Performance Microprocessor Implementations:
    • J. M. Tendler, J. S. Dodson, J. S. Fields, Jr. H. Le, B. Sinharoy. "Power4 System Microarchitecture." IBM Journal of Research and Development, January 2002. Available Here.