No guarantees this page gets updated in a timely manner. Lab descriptions are to be picked up in class.

Lab Assignments:

Lab 1:  8-bit Instruction Set Architecture. TYPO ALERT: In question 17 (program 2 discription), "bit positions 0, 4, 5, 7" should read "bit positions 0, 3, 4, 7".
Lab 2:  8-bit CPU Internals. Here are the other class handouts that we talked through: schematic, timing.
Lab 3:  8-bit CPU. Creating memories is significantly complicated by the fact that the Xilinx webpack does not include the coregen module. Therefore, you need to follow these instructions very carefully. Because some of the VHDL code, especially to initialize memory, can be long, here is the Word file, so that you can cut and paste. Also, we still don't allow you to use VHDL, except for the RAM and ROM as described here.
Lab 4:  Branch Simulator.  Here is the tutorial on branch predictors.