Follow this link to the CSE 140L Webpage

CSE 140 Fall 2004 

(Lecture- Tue/Thu: 5:00 - 6:20pm, HSS 1330
Discussion- Mon: 3:00 - 4:20pm, CSB 002)

Instructor:

Alex Orailoglu, alex@cs.ucsd.edu

Office Hours:
Wednesday 1:30 pm - 2:30 pm
Thursday 1:30 pm - 2:30 pm

AP&M 4840

Teaching Assistants

Baris Arslan

barslan@cs.ucsd.edu

Monday 11:00 -1:00 pm

Monday 5:00 -6:00 pm

AP&M 4819

Chengmo Yang

c5yang@cs.ucsd.edu

Ming Woo-Kawaguchi

mwookawa@ieng9.ucsd.edu 

Tuesday 2:00 - 4:00 pm

AP&M 4819

 

 

Announcements:
*Classes start on Thursday September 23rd in HSS 1330.

*Please check back frequently to see the updated announcements, homeworks, and handouts.

*Please direct all course-related emails to mwookawa@ucsd.edu

*All midterm and quiz grades to date are posted on WebCT. If you have a question about your grade or there is an inconsistency, please email course staff.

*The CSE140 final exam will be held on Tuesday, 12/7, in HSS 1330 at 7-10pm. The exam will be cumulative; ie, it will cover all material covered by the course.

*FINALS WEEK OFFICE HOURS:
Baris Arslan - Mon 11-1, 5-6pm APM 4819
Chengmo Yang (review session) - Tue 3:00-4:20 HSS 2321
Ming Kawaguchi - Tues 4:30-6:30pm APM 4819
GOOD LUCK!

 

Handouts:

 

Class Notes:

 

Evaluation:

 

%

Midterm1

25%

Midterm2

25%

Final

50%

Unannounced quizzes:

2.5% each

 

 

Homeworks:

Errors in the text book:
  • Fig 2.10 part C: excess 1032 should be excess 1023
  • Fig. 3.3: xi, yi -> si delay should be 7.6, NOT 7.2
  • Fig. 3.4 xi, yi -> ci+1 delay should be 3.2, NOT 4.2
  • Fig. 3.5 AOI 3-wide, 2-inputs, marked delay on the schematic should be 2.2 not 2.0 Consequently all 4.4 ns delay paths in summary should also be 4.6
  • Page 144, QM tables, subcubes (8,9) should be 1 0 0 _ instead of _ 0 0 1. Similarly, subcubes 9,13 and 13,15 have the same mistakes of wrong placement of the dash
  • Table 5.2: The delays marked as x0,y0 are actually from any x,y input, the worst case delay actually comes from x3,y3 because the generate signal for the CLA block does not depend on the propagate signal of x0,y0
  • Table 5.2: x0,y0 -> c8 delay should be 15.8, NOT 16.2
  • Table 5.2: x0,y0 -> c12 delay should be 16.6, NOT 17