In this lab, we will learn how to study and build different types of adders.
Part 1. 4-bit Adder/Subtractor with Overflow
(Please read again the description of this part as it has been changed.)
Build a 4-bit Adder/Subtractor with an Overflow Indicator.
Assume the operands A and B, and the operation result S are all 4-bit 2's complement numbers.
That is, they can count in the range of -8 ... 7. An overflow occurs if the result S is outside of this range.
A 4-bit 2's complement Adder/Subtractor with an Overflow Indicator looks like this:
For this part of the lab, do the following:
| i. | Implement the adder/subtractor with overflow circuit shown above. Explain how it works. |
| ii. |
Simulate the circuit using Xilinx.
Show these 8 simulation cases: 4 + 5, 4 - 3, 6 - 1, 5 + 7, 6 + 3, 6 - 4, 2 + 6, 4 - 6. Note that all operands are positive numbers (e.g. 4, 5). If the simulation case uses a "+", please show an addition. If the simulation case uses a "-", please show a subtraction. Note that the result may be a negative number (e.g. 4 - 6 = -2). Simulation results should include the Overflow output as well. |
Part 2. 4-bit Carry Lookahead Adder
Build a 4-bit carry lookahead adder
| i. | Design and implement the circuit (describe how carry lookahead works and how you derive the final circuit layout) |
| ii. | Build and simulate the circuit using Xilinx. (show the following 8 cases: 15+1, 5+7, 10+5, 2+7, 7+12, 9+3, 2+4, 15+15). |
| iii. | Describe the advantages and disadvantages of carry lookahead adder in relation to ripple adder. Describe in terms of speed (indicate how many levels in the critical path) and area. |
Part 3. 8-bit Carry Select Adder
Build an 8-bit carry select adder
| i. | Design and implement the circuit (describe how carry select adder works and how you derive the final circuit layout) |
| ii. | Build and simulate the circuit using Xilinx (show the following 8 cases: 186+102, 50+151, 114+196, 111+129, 68+29, 213+88, 98+93, 167+106). |
| iii. | Describe the advantage and disadvantage of carry select adder. Describe how many gate levels the critical path contains. |
Part 4. Introducing D Flip Flop
Build a 3-bit shift register using positive edge-triggered D Flip Flops ("FD" in Xilinx).
Please use the design in pg. 271 of Gajski's book, but build a 3-bit adder instead of 4-bits.
e.g. Let Q2Q1Q0 = 011. Let IL = 0. And let Shift = 1. (Shift = 0 means no change.)
Then the result after shifting is 001.
| i. | Design and implement the circuit. |
| ii. | Build and simulate the circuit using Xilinx. Show at least 8 clock cycles or data. |
Report
Title page:
- Names of students and due date.
- Title of the lab and objective.
- A brief description of each person's contribution.
- Part 1 i, ii
- Part 2 i, ii, iii
- Part 3 i, ii, iii
- Part 4 i, ii
- Include this printout at the end of the lab report
90% will based on the completeness and correctness of the report. 10% will based on the neatness, organization, and following instruction of the report format.