Frequently Asked Questions

• Q: My simulation isn't working, how do I fix it?
  A: Please look at the main/first Xilinx window, the bottom part of that displays any error messages that your schematic editor or simulator send. Although the messages may not be terribly helpful in telling you what's wrong, they usually can give you a decent idea where the problem is located.

• Q: How do I use the clock in Xilinx?
  A: According to a helpful student, you should link the clock to B0-8 in 'add simulator'. The number indicates the frequency, and then the clock will oscillate automatically. You must also be in timing mode instead of function mode.

• Q: What's the problem when a gray bar is shown as one of my outputs for a Xilinx simulation?
  A: Usually one of two things: either you don't have all of your gate inputs connected to wires, or you don't have the schematic saved or added to the project. To make sure you have your gate inputs connected, there should be wires going into each one. Even if you line up a gate output directly with a gate input, Xilinx will not realize they are really connected unless you run a wire from the output of one to the input of another.

• Q: Do I have to do the lab with a partner, or can I work alone?
  A: You don't have to work with a partner for the first lab, but your report will be graded according to the same standard as those who do, so you might want to save yourself some work by finding a partner. After the first lab, you should have had time to find a partner, and labs 2-4 must be done in pairs. If you have trouble finding a partner, please email me and I'll match you up with someone. And you cannot work in groups of more than two.