Additional problem for homework Set 2

Critical Path Analysis
Find the critical path through the sets of gates. You should draw the gate layout as a part of your answer. Use the following delays:

2 input NAND - 2ns
NOT - 1ns
XOR and 3 input NAND - 4ns

Your answer should be of the form:
Critical Path = a-> h-> t-> .... etc
Total delay = 2 + 2 + 2 + ... etc

A) Inputs are a, b, c, d, e and the final outputs are j and k.

f = NAND (a, b)
p = NOT (c)
h = NAND (f, p)
g = NOT (d)
i = NAND(g, c)
k = NAND (d, e)
j = NAND (h, i)

B) Inputs are a, b, c, d, e, f, g, h, i and the final outputs are t and p.

j = XOR (a, b)
k = NAND (c, d)
s = XOR (e, f)
n = NAND (g, h, i)
t = XOR(j, k)
m = NAND (k, s)
p = NAND (m, n)