Lab 4 Sample Output
I have included some sample output so that you can make sure that your lab does what it is supposed to do. You can also see how you MUST combine your data in the simulation (flatten and use BINARY as the encoding method). Please note that if you use this specific example for the Functional Simulation of your report, you will receive 0 POINTS for that section!!!!
  1. Init
    1. 3 bit Instruction is 000 (I2=I1=I0=0)
    2. 4 bit data is don’t care (can be anything, output is same)
    3. Register 1 input is don’t care
    4. Register 2 input is don’t care
    5. Register 3 input is don’t care
    6. Register 1 output (contents) becomes 0000
    7. Register 2 output (contents) becomes 0000
    8. Register 3 output (contents) becomes 0000

  2. Move1
    1. 3 bit Instruction is 001 (I2=I1=0, I0=1)
    2. 4 bit data is the value to be stored in R1, in this case 1101
    3. Register 1 input is 4 bit data, in this case 1101
    4. Register 2 input is don’t care
    5. Register 3 input is don’t care
    6. Register 1 output (contents) becomes 4 bit data, in this case 1101
    7. Register 2 output (contents) is unchanged
    8. Register 3 output (contents) is unchanged

  3. Move2
    1. 3 bit Instruction is 010 (I2=0, I1=1, I0=0)
    2. 4 bit data is the value to be stored in R2, in this case 1011
    3. Register 1 input is don’t care
    4. Register 2 input is 4 bit data, in this case 1011
    5. Register 3 input is don’t care
    6. Register 1 output (contents) is unchanged
    7. Register 2 output (contents) becomes 4 bit data, in this case 1011
    8. Register 3 output (contents) is unchanged

  4. Add
    1. 3 bit Instruction is 100 (I2=1, I1=I0=0)
    2. 4 bit data is don’t care
    3. Register 1 input is don’t care
    4. Register 2 input is don’t care
    5. Register 3 input is the sum of Register 1 output and Register 2 output in this case, 1000 (1101+1011)
    6. Register 1 output (contents) is unchanged, in this case 1101
    7. Register 2 output (contents) is unchanged, in this case 1011
    8. Register 3 output (contents) becomes the sum of R1 and R2, in this case 1000
    9. Flag is set if an overflow has occurred, in this case true

  5. Store
    1. 3 bit Instruction is 011 (I2=0, I1=I0=1)
    2. 4 bit data is don’t care
    3. Register 1 input is don’t care
    4. Register 2 input is output from register 3, in this case 1000
    5. Register 3 input is don’t care
    6. Register 1 output (contents) is unchanged
    7. Register 2 output (contents) becomes register 3 output, in this case 1000
    8. Register 3 output (contents) is unchanged, remains 1000

  6. Shift
    1. 3 bit Instruction is 101 (I2=1, I1=0, I0=1)
    2. 4 bit data – first two bits are the number of bits to shift left by, last two bits are don’t cares, in this case, since the input is 1011, we will shift by 2 bits since 10 represents the number 2 in binary
    3. Register 1 input is don’t care
    4. Register 2 input is don’t care
    5. Register 3 input becomes the shifted output from Register 2, in this case 0010
    6. Register 1 output (contents) is unchanged
    7. Register 2 output (contents) is unchanged
    8. Register 3 output (contents) becomes the shifted output from Register 2, 0010

  7. Comp
    1. 3 bit Instruction is 110 (I2=1, I1=1, I0=0)
    2. 4 bit data – don’t care
    3. Register 1 input is don’t care
    4. Register 2 input is don’t care
    5. Register 3 input is don't care
    6. Register 1 output (contents) is unchanged
    7. Register 2 output (contents) is unchanged
    8. Register 3 output (contents) is unchanged
    9. Flag bit is true if R1 is greater than or equal to R2. In this case, R1 (1101) is greater than R2 (1000) so the flag is set to true

  8. Mask
    1. 3 bit Instruction is 111 (I2=1, I1=1, I0=1)
    2. 4 bit data – don’t care
    3. Register 1 input is don’t care
    4. Register 2 input is don’t care
    5. Register 3 input becomes R1 ANDed with R2, in this case 1000 (1101 AND 1000 = 1000)
    6. Register 1 output (contents) is unchanged, 1101
    7. Register 2 output (contents) is unchanged, 1000
    8. Register 3 output (contents) becomes R1 ANDed with R2, in this case 1000