Comments on grading lab 1. -Generally most labs were missing something or lacking. I was VERY lenient and generous in grading these since this was the first experience for most of you with Xilinx. However please do improve upon these in future labs, as they will not be graded as easily (And I won't even be grading them, the other tutors will, and Hansen promises to grade HARD for lab 3).

Some general issues:

-In general, I was very lenient on grading. I gave out a lot of 10's that would at most rate a 9 or 8.5 if you were taking this in past quarters. And the 9's and 9.5's I did give out would be at most a 8 or 7.5. Please turn in what is asked from you! I did not dole out extra credit points to groups that turned in elaborate reports. For future labs, the graders will be much harder. Generally we want what is asked on the lab sheet, and usually this includes schematics of ALL your circuits you used, and enough timing simulations / test cases to show that your circuit works. Points will be docked in future labs if you do not provide sufficient work on either. If you have any questions or comments or want me to regrade your lab, please email me tweng@ucsd.edu. BTW if you got comments like 'you deserve a 10' or "i would give you a 11', that tends to mean you are on the right track as to how to approach these labs. If not and you still got a 10, def. improve on your labs for the future ones.

-Most of you also were pretty lacking in your timing simulations. You need more than one test case to show your circuit was working. I generally did not dock points for this, but for future labs, include at least four and preferably more test cases for ALL your circuits to show that your circuits work. And even worse, some of you still put really lousy test cases like all 0s and then all 1s. This seriously won't cut it in future labs. We WILL be docking points for really poor timing simulations that don't prove or show anything (this accouts for nearly all of you!).

-ALMOST all of you did not even label your test cases. It is very helpful both to the grader and to you (for checking that your circuit works) to write down what you are doing for your test cases.

-In terms of things actually working.. well most of you had working circuits, even though you did not include enough test cases to actually show that. The circuits though are very trivial, the whole point of this lab was to get you acquainted with Xilinx. Those that did not I tended not to dock too many points, but make sure you become very familiar with Xilinx ASAP and know how to make a working circuit and know how to test it properly. It's clear that a few of you do not know what a working timing simulation looks like.

General issues on part 2 (Adders)

-Most of you did not include the half adder schematic. Even though we do not ask for it specifically, you need to include ALL schematics you use, even if it is just a macro for a bigger circuit. I did not dock points for this, but rememember, include ALL your circuits!

-A few of you did not include the 4 bit adder worst case. This was given to you in class and emphasized as well. I docked a small amount for missing it.

General issues on part 3 (Subtractor)

-Many of you were very sloppy with your labeling. You left your subtractor with labels of Sum and Cin, when you meant Diff and Bin. And some of you had test cases with labels that did not even match your schematic. I did not dock points for this, giving all of you the benefit of the doubt and letting it slide, but it's sloppy and confusing, among other things...

-Speaking of labeling, many of you opted to create a full sub from two half subs. You need to be very careful what you label Bin and x and y because it does matter. Some of you just left it with wierd names like q, r, t and that makes it hard to see what's going on.

-Most of you did not have a correct worst case delay for the subtractor, and many of you did not even include it period. I did not dock points for this since unlike the adder, it was not given to you point blank in class... but yeah for future labs make sure you do ALL the requirements.

-Some of you did not include your schematics for other circuits (other than half adder). For example some did not include the full subtractor circuit, instead just including the full subtractor box as a macro. You cannot just submit a magical black box! (The same is true for your half adder that most of you did not turn in, but since it was part of the tutorial I let that slide). I did dock a little bit for missing schematics if I was convinced that your circuit did indeed work. Please be more careful in the future!

General comments on part 4 (MUX)

-Some of you did not include the description for your multiplexor. That was specifically assigned! I docked very little if you missed it completely, but still.. considering it was the first two parts of your part 4...

-A couple of you for your 4:1 MUX had two input terminal for the same input (usually s0). You can connect them to the same input terminal. It looks more clear that way.

-A few of you do not realize that there is something called an inverter (INV) that functions as a not gate. It was cute though seeing so many different ways of implementing a not gate with ANDs and ORs and XORs.

Regrades: If you would like me to regrade your lab, I'll be happy to look over it again. HOWEVER I will regrade it with past quarters (and next labs) criteria, which means that almost certainly your lab grade will go down (a lot) instead of up.. Especially since I doled out so many 9s,9.5s,10s. If there was an honest mistake on my part (I totally did not see that you had a worst case and marked you down for it) then that of course I will just give you points back for that.

Sample outline of what lab 1 could have looked like:

In case you were wondering, here is an outline of what a good lab 1 would have... (Yeah I know this would have been more useful prior but it should be pretty obvious what we are looking for..).
- A brief summary of Xilinx, like "First start new project and then new schematic.. etc"
-Your half adder and full adder circuits, followed by a few timing simulations that are WELL LABELED and demonstrate that your full adder works, w/ delay. So perhaps show 0+0 w/ cin of 0 = 0 and 0, 0+1+0 = 1 and 0, 1+1+0 = 0 and 1, 1+1+1 = 1 and 1. Label this of course on your timing simulation to show what you are trying to do.
-Your 4-bit adder schematic, followed by a few timing simulations that show that it works, well labeled of course, and then your worst case timing simulation, with delay labeled.
-Your full subtractor schematic, followed by timing simulations for that, well labeled, with delay labeled. -Your 4 bit subtractor schematic, followed by timing simulatoins, and then with the worst case subtractor delay.
-A good definition of a MUX, and how the inputs relate to the outputs (a truth table for this would be good).
-How you came up with your MUX, ie, "We realized we needed 4 inputs, so we needed two MUXes for that, and we also realized we needed a third MUX to select the two initial MUXes, etc".
-Your 4:1 MUX schematic, along w/ a few good test cases showing that it works.