CSE 140L Hardware Lab Four, Fall 2002



C.K. Cheng

System Design using Datapath and Control Subsystems
Due Date: December 3, 2002
Objective
In this lab, we will build a simple system using datapath and control subsystems. We use buses and standard modules as basic building blocks for the design. For this project, we use FPGA Family: XC400E, Part: 4003EPC84 and Speed: 1.

The Project
Design a simple system that can perform addition, shift, comparison, and masking. The system reads a 7-bit value as input (3-bit instruction set & 4-bit data). There are three 4-bit registers R1, R2, and R3. Registers R1 and R2 store the data. Register R3 presents the result of the calculations. There is also a 1-bit flag for overflow and comparison. We list the specification of the instructions:
Command 3-bit Instruction 4-bit Data Description
1. Init 000 XXXX Initialize all registers, ie R1=R2=R3=(0,0,0,0)
2. Move1 001 aaaa Put aaaa value into register R1
3. Move2 010 bbbb Put bbbb value into register R2
4. Store 011 XXXX take the previous result in R3 and store into register R2
5. Add 100 XXXX Add contents in R1 and R2. Present the result at R3 and output overflow flag
6. Shift 101 aaXX Take the content in R2 and left shift by aa bits, then store the result in R3
7. Comp 110 XXXX Compare the contents of R1 and R2. The flag bit is true if R1 is greater than or equal to R2. Otherwise it is false
8. Mask 111 XXXX Mask (AND-ing) R1 and R2. Present the result in R3
* For 4-bit data, X is Don't Care.
**Note that register R1 holds its content except for instructions 1 and 2. Register R2 holds except for instructions 1, 3, and 4. Register R3 holds except for instructions 1, 5, 6, 8.


Report
  1. Title Page:
    1. Names of students and due date
    2. Title of the lab and objective
    3. A brief description of each person's contribution
  2. Content:
    1. Schematic diagram of the design - must use buses
    2. ABEL code of the control subsystem using one truth table
    3. Layout of the design (FPGA)
    4. Functional simulation of instructions. Demonstrate the content of the input and output of each of the 8 instructions. Label and explain the data before and after each operation.
    5. Discussion of the verification. Show the reason why we are confident that the system can function properly. List the process needed for the proof. Use less than 30 words.
    6. Illustrate the worst delay path between registers with timing simulation.